AM79C983A datasheet(35/60 Pages) AMD

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Am79C983A

PRELIMINARY

Pn/AUI/RAUI/EP

Runts with Valid FCS Interrupt

masked (disabled)

Runts

with

Valid

FCS

Interrupt enabled

Link Status Change Interrupt Enable

Address:

1110 0010

Setting any of the bits in this register causes the INT pin

to be driven when there is a change in the Link Test

state of the corresponding port. The corresponding sta-

tus bit in the Link Test State Change Register is set to 1.

TPn/SPn

Link Status Change Interrupt

masked (disabled)

Link Status Change Interrupt

enabled

Loopback Error Change Interrupt Enable

Address:

1110 0011

Setting a bit in this register causes an interrupt to be

generated when the IMR2 device senses a change in the

Loop Back Error condition on the corresponding port.

Pn/AUI/RAUI

Loopback Error Change Interrupt

masked (disabled)

1 Loopback

Error

Change

Interrupt enabled

Polarity Change Interrupt Enable

Address:

1110 0100

Setting a bit in this register causes an interrupt to be gener-

ated when the polarity of the connected port is changed.

TPn/SPn

Polarity

Change

Interrupt

masked (disabled)

Polarity

Change

Interrupt

enabled

SQE Test Error Change Interrupt Enable

Address:

1110 0101

Setting a bit in this register causes an interrupt to be

generated when the IMR2 device senses a change in

the SQE Test Error condition at a port. This occurs

when an attached MAU has SQE Test enabled. A new

interrupt is generated when a condition change is

sensed by the IMR2 device.

Pn/AUI/RAUI

SQE

Test

Error

Change

Interrupt masked (disabled)

SQE

Test

Error

Change

Interrupt enabled

Source Address Changed Interrupt Enable

Address:

1110 0110

This register enables interrupts caused by a mismatch

between the source address of an incoming packet and

either the Last Source Address Register or the Preferred

Source Address Register. If Last Source Address Lock

is not set and the packet is a valid packet, a mismatch

between the source address and the Last Source

Address Register also causes the new source address

to be written into the Last Source Address Register.

Pn/AUI/RAUI/EP

Source

Address

Changed

Interrupt masked (disabled)

Source

Address

Changed

Interrupt enabled

Intruder Interrupt Enable

Address:

1110 0111

This register enables interrupts to be generated when the

source address of an incoming packet does not match the

Preferred Source Address Register on the corresponding

port. The corresponding interrupt can be interpreted as

an attempt by an intruder to gain access to the network.

The management system can then take appropriate ac-

tion, such as disabling the corresponding port.

Pn/AUI/RAUI

Intruder Interrupt masked (disabled)

Intruder Interrupt enabled

TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0

SP3 SP2 SP1 SP0 TP11 TP10 TP9 TP8

Byte 0

Byte 1

D Port Read/Write

MSB

LSB

RAUI

AUI P11 P10 P9

D Port Read/Write

Byte 0

Byte 1

LSB

MSB

TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0

SP3 SP2 SP1 SP0 TP11 TP10 TP9 TP8

Byte 0

Byte 1

D Port Read

MSB

LSB

RAUI

AUI P11 P10 P9

D Port Read/Write

Byte 0

Byte 1

MSB

LSB

RAUI

AUI P11 P10 P9

D Port Read/Write

Byte 0

Byte 1

MSB

LSB

RAUI

AUI P11 P10 P9

D Port Read/Write

Byte 0

Byte 1

MSB

LSB

AM79C983A Datasheet(PDF) 35 Page - Advanced Micro Devices

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