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AM79C983A Datasheet(PDF) 18 Page - Advanced Micro Devices |
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AM79C983A Datasheet(HTML) 18 Page - Advanced Micro Devices |
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18 / 60 page ![]() 18 Am79C983A PRELIMINARY a. Standard reconnection algorithm—A data packet longer than 512-bit times (nominal) is transmitted or re- ceived by the partitioned port without a collision. b. Alternate reconnection algorithm—A data packet longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision. Basic Management Functions Repeater Management The IMR2 management functions are a super-set of the those provided by the AMD’s IMR+/HIMIB device chipset. The IMR2 device contains the complete set of repeater and port functions as defined in ANSI/IEEE 802.3, Repeater Management Standard, (Section 19). All mandatory and optional capabilities are supported. These include the Basic Control, Performance Monitor- ing, and Address Tracking packages. Additionally, Node Address Mapping, MAU Management specific functions, and intrusion protection functions are in- cluded. Support is also provided for the RMON MIB RFC 1757. All information is stored in registers which can be ac- cessed through the Microprocessor Interface (Node Processor Port). The register location is defined by a register bank and an address within that register bank. Address and data of the registers are multiplexed using the C/D pin. The register address is selected by writing to the Node Processor Port with C/D HIGH. The regis- ter data is selected by writing or reading to the Node Processor Port with C/D LOW. Many of the registers are larger than 1 byte. For these registers, consecutive accesses to register data (equal to the number of bytes in the register) are required. The order is LSByte to MSByte. For a write operation, if the address changes before all the bytes are written, the register is not changed to the new value. The Status Register is accessed by reading the Node Processor Port with the C/D pin HIGH. This reduces the number of operations necessary to access the Status Register. All bit fields are ordered such that the left most bit is the most significant bit. Unused register banks, ports and register numbers are reserved and should not be ac- cessed as this may cause device malfunction. When specifying the register bank or port number, the follow- ing format is used: P4:0 represent the Register Bank or Port Number, or- ganized as follows: P = P4 P3 P2 P1 P0 P Port/Register Bank 0 Repeater Registers 1 Interrupt Registers 2 Interrupt Control Registers 3 Port Control Registers 4 Port Status Registers 5 RMON Registers 7 Packet Report Registers 16- 30 Port Attributes The register to be accessed for reading or writing is specified by writing the following control byte to the C register: R = R4 R3 R2 R1 R0 Figure 1 shows the Management Register Map, and Table 1 shows register banks and register assignments within the register banks. RMON Remote monitoring (RMON) functions are designed to give the management system the capability to remotely monitor the hub for diagnostic purposes. The rules for RMON are described in the RMON MIB (as of this writing IETF RFC1578). The IMR2 device provides direct support for both the statistics and history object groups. Indirect support is provided for the alarm, host, hostTopN, event, and ma- trix groups. Direct support is provided via the RMON register set and relevant attribute registers. Indirect support is provided through the Packet Report Port. Packet Reports The IMR2 device generates status information on every packet that it repeats. The data is transmitted over the Packet Report Port. The data format consists of the beginning of the packet followed by a packet tag and statistical data on the packet. 0 0 0 P4 P3 P2 P1 P0 C Port Write MSB LSB 1 1 1 R4 R3 R2 R1 R0 C Port Write MSB LSB Preamble DA SA T/L Packet Data Var. Length Tag & FCS Port No., New Status |
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