AM79C983A datasheet(17/60 Pages) AMD

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Am79C983A

PRELIMINARY

FUNCTIONAL DESCRIPTION

Overview

The Am79C983A Integrated Multiport Repeater 2 de-

vice provides a system-level solution to designing IEEE

802.3 managed repeaters. It includes 12 pseudo AUI

(PAUI) ports for single-ended connections to external

transceivers. The IMR2 device interfaces directly with

AMD's Am79C988A Quad Integrated Ethernet Trans-

ceiver (QuIET) device for 10BASE-T implementations.

The PAUI ports can be turned off individually to enable

port switching applications. In addition, the IMR2 de-

vice has a standard AUI port and a reversible AUI

(RAUI) port for a direct connection to a MAC.

The IMR2 device provides a Hardware Implemented

Management Information Base (HIMIB) which contains

all of the necessary counters, attributes, actions, and

notiﬁcations speciﬁed by Section 19 of the IEEE 802.3

standard. Support for an RMON MIB, as speciﬁed by

the Internet Engineering Task Force (IETF) RFC 1757,

is also provided. Direct support is from an RMON Reg-

ister Bank. Additional support is provided by the Packet

Report Port, which supplies packet information that can

be used in conjunction with a microprocessor to derive

various RMON MIB attributes.

Basic Repeater Functions

The IMR2 repeater functions are summarized below.

An over view of IMR2 management functions is

presented under

Basic Management Functions.

Repeater Function

If any single network port of a repeater system senses

the start of a valid packet on its receive lines, the IMR2

device will retransmit the received data to all other en-

abled network ports unless a collision is detected. The

repeated data will also be presented on the DAT line of

the expansion bus to facilitate designs utilizing multiple

IMR2 devices. The IMR2 device fully complies with

Section 9.5.1 of the IEEE 802.3 speciﬁcations.

Signal Regeneration

When retransmitting a packet, the IMR2 device en-

sures that the outgoing packet complies with the IEEE

802.3 speciﬁcation in terms of preamble structure.

Data packets repeated by the IMR2 device will contain

a minimum of 56 preamble bits before the Start of

Frame Delimiter.

The IMR2 device, by virtue of its internal Phase Lock

Loop and Manchester Encoder/Decoder, will ensure

correct regeneration of the repeated signal at its PAUI

and AUI outputs. If the outputs of the IMR2 device are

connected to QuIET device transceivers, the 10BASE-T

outputs of the QuIET devices will meet the IEEE 802.3

signal symmetry requirements. If other types of trans-

ceivers are used, the signal characteristics will depend,

in part, on the transceiver.

Jabber Lockup Protection

The IMR2 chip implements a built-in jabber protection

scheme to ensure that the network is not disabled due

to transmission of excessively long data packets. This

protection scheme will automatically interrupt the

transmitter circuits of the IMR2 device for 96-bit times,

if the IMR2 device has been transmitting continuously

for more than 65,536 bit times. This is referred to as

MAU Jabber Lockup Protection (MJLP). The MJLP

status for the IMR2 chip can be read from the

Repeater Status Register.

Collision Handling

The IMR2 chip will detect and respond to collision con-

ditions as speciﬁed in the IEEE 802.3 speciﬁcation. A

multiple IMR2 device repeater implementation also

complies with the speciﬁcation because of the inter-

IMR2 chip status communication provided by the ex-

pansion port. Speciﬁcally, a repeater based on one or

more IMR2 devices will handle correctly the transmit

collision and one-port-left collision conditions as spec-

iﬁed in Section 9 of the IEEE 802.3 speciﬁcation.

Fragment Extension

If the total packet length received by the IMR2 device is

less than 96 bits, including preamble, the IMR2 chip will

extend the repeated packet length to 96 bits by ap-

pending a Jam sequence to the original fragment. Note

that in a few cases, it is possible for the IMR2 device to

generate a sequence 97 bits in length when the expan-

sion bus is operated in the asynchronous mode.

Auto Partitioning/Reconnection

Any of the IMR2 ports can be partitioned under exces-

sive duration or frequency of collision conditions. Once

a port is partitioned, the IMR2 device will continue to

transmit data packets to a partitioned port, but will not

respond (as a repeater) to activity on the partitioned

port’s receiver. The IMR2 chip will monitor the port and

reconnect it once certain criteria indicating port “well-

ness” are met. The criteria for reconnection are speci-

ﬁed by the IEEE 802.3 standard. In addition to the

standard reconnection algorithm, the IMR2 device im-

plements an alternative reconnection algorithm which

provides a more robust partitioning function. Each port

is partitioned and/ or reconnected separately and inde-

pendently of other network ports.

Either one of the following conditions occurring on any

enabled IMR2 device network port will cause the port

to partition:

a. An SQE signal active for more than 2048 bit times.

b. A collision condition occurs during each of 32 con-

secutive attempts to transmit to that port.

Once a network port is partitioned, the IMR2 device will

reconnect that port if the following is met:

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