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AM79C983A Datasheet(PDF) 38 Page - Advanced Micro Devices |
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AM79C983A Datasheet(HTML) 38 Page - Advanced Micro Devices |
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38 / 60 page ![]() 38 Am79C983A PRELIMINARY are ignored. This feature is useful when implementing port switching. The IMR2 device connected to the QuIET device serial interface will still report correct status on the Link and Polarity LEDs. The ports default to the XENA value on reset. Pn/AUI/RAUI 0 Isolate the corresponding port 1 Connect the corresponding port Note: If a port is isolated during an incoming or transmit- ted packet, repeating the packet is immediately stopped. If a port is connected during an incoming packet, the ac- tual connection is delayed until after the end of the packet. If a port is connected while the IMR2 device is repeating a packet, the connection is made immediately. Extended Distance Enable Address: 1110 1000 Setting a bit on this register lowers the input threshold on RXD of the corresponding QuIET transceiver. This allows the use of a twisted pair cable longer than 100 meters. This register is only in effect if the correspond- ing port is connected to a QuIET device. On reset, this register defaults to Extended Distance Option disabled. TPn/SPn 0 Extended Distance Option disabled 1 Extended Distance Option enabled Automatic Last Source Address Intrusion Control Address: 1110 1001 Automatic Intrusion Control disables a port automati- cally when a valid packet (no errors) is received with a source address which is not a valid address for that port. Before a bit on this register is set, the correspond- ing Last Source Address Register should contain a valid address for that port. On reset, this register de- faults to Automatic Intrusion Control with Last Source Address disabled. See note under Automatic Preferred Source Address Intrusion Control. Pn/AUI/RAU 0 Automatic Intrusion Control with Last Source Address disabled 1 Automatic Intrusion Control with Last Source Address enabled Automatic Preferred Source Address Intrusion Control Address: 1110 1010 Automatic Intrusion Control disables a port automatically when a valid packet (no errors) is received with a source address which is not a valid address for that port. Before a bit on this register is set, the corresponding Preferred Address register should contain a valid address for that port. On reset, this register defaults to Automatic Intrusion Control with Preferred Source Address disabled. Pn/AUI/RAUI 0 Automatic Intrusion Control with Preferred Source Address disabled 1 Automatic Intrusion Control with Preferred Source Address enabled Note: The Automatic Preferred Source Address Intru- sion Control Register and the Automatic Last Source Ad- dress Intrusion Control Register work together. If intrusion on a port is not enabled on either register, intrusion control is not performed for that port. If intrusion on a port is en- abled on only one of the intrusion control registers, intru- sion control is based on the corresponding enabled register. If intrusion on a port is enabled on both intrusion control registers, the port is disabled if the source address fails to match both the Last Source Address Register and the Preferred Source Address Register. Last Source Address Lock Control Address: 1110 1011 Whenever the source address of an incoming packet is different from the Last Source Address Register, the new source address is written into the Last Source Ad- dress Register. Setting a bit on this register disables automatic updating of the Last Source Address Regis- ter based on the last received packet. The Last Source Address Register can still be written into via the node processor interface. On reset, this register defaults to Last Source Address Lock disabled. Note that a re- peater that uses Last Source Address Lock Control will not comply with IETF RFC 1516. P7 P6 P5 P4 P3 P2 P1 P0 0 0 RAUI AUI P11 P10 P9 P8 D Port Read/Write Byte 0 Byte 1 MSB LSB TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 SP3 SP2 SP1 SP0 TP11 TP10 TP9 TP8 Byte 0 Byte 1 D Port Read/Write MSB LSB P7 P6 P5 P4 P3 P2 P1 P0 0 0 RAUI AUI P11 P10 P9 P8 D Port Read/Write Byte 0 Byte 1 MSB LSB P7 P6 P5 P4 P3 P2 P1 P0 0 0 RAUI AUI P11 P10 P9 P8 D Port Read/ Write Byte 0 Byte 1 MSB LSB P7 P6 P5 P4 P3 P2 P1 P0 0 EP RAUI AUI P11 P10 P9 P8 D Port Read/Write Byte 0 Byte 1 MSB LSB |
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