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TPS65950 Datasheet(PDF) 64 Page - Texas Instruments

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Part # TPS65950
Description  Integrated Power Management/Audio Codec
PDF  171 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS65950 Datasheet(HTML) 64 Page - Texas Instruments

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VBAT
DEVOFF(register)
NRESPWRON
REGEN
32K
OUT
CLK
DCDCs
LDOs
SYSEN
HFCLKOUT
CLKEN
NEXT_Startup_event
18 s
m
1.2ms
1.2ms
1.2ms
18 s
m
18 s
m
18 s
m
3.42msbeforedetectionofstartingevent
126 s
m
032-013
TPS65950
SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011
www.ti.com
NOTE: All timings are typical values with the default setup (depending on the resynchronization between power domains,
state machinery priority, etc.).
Figure 4-12. Power-Off Sequence in Master Modes
If the value of the HF clock is not 19.2 MHz (with the values of the CFG_BOOT HFCLK_FREQ bit field set
accordingly), the delay between DEVOFF and NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided
by two (approximately 9
μs). This is caused by the internal frequency used by power STM switching from
3 to 1.5 MHz if the HF clock value is 19.2 MHz.
The DEVOFF event is PWRON falling edge in slave mode and DEVOFF internal register write in master
mode.
64
Power Module
Copyright © 2008–2011, Texas Instruments Incorporated
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