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TPS65950 Datasheet(PDF) 21 Page - Texas Instruments |
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TPS65950 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 171 page  TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 2-2. Signal Description (continued) Configuration By Default After Reset Released Signal Unused Module Description Type(1) Ball Name Features(2) Internal Signal Type(1) Pull or Not SYSEN System enable output OD/I C13 SYSEN OD PU Floating CLKEN Clock enable O C6 CLKEN O Floating CLKEN2 Clock enable 2 O D7 CLKEN2 O Floating CLKREQ Clock request I G10 CLKREQ I PD GND INT1 Output interrupt line 1 O F10 INT1 O Floating INT2 Output interrupt line 2 O F9 INT2 O Floating Output control the NRESPWRON NRESPWRON O A13 NRESPWRON O Floating of the application processor Input, detect user action on the NRESWARM I B13 NRESWARM I GND reset button Input, detect a control command to PWRON I A11 PWRON I VBAT start or stop the system CONTROL NC Not connected B14 NC Floating NSLEEP1 Sleep request from device 1 I P7 NSLEEP1 I GND NSLEEP2 Sleep request from device 2 I G9 NSLEEP2 I GND CLK256FS Control for 256 × FS CLK output O D13 CLK256FS O Floating Digital voltage scaling linked with VMODE1 I F8 VMODE1 I GND VDD1 BOOT0 Boot pin 0 I K11 BOOT0 I PD N/A BOOT1 Boot pin 1 I J11 BOOT1 I PD N/A REGEN Enable signal for external LDO OD A10 REGEN OD PU Floating Security and digital rights MSECURE I H8 MSECURE I N/A management VREF Reference voltage Power N16 VREF Power N/A VREF Analog ground for reference Power AGND N15 AGND Power GND GND voltage GND NC Not connected Signal not C4 Floating functional(4) I2C.SR.SDA I/O SmartReflex I2C data I2C Digital voltage scaling linked with SmartReflex VMODE2 I VDD2 D6 VMODE2 I GND I2C.SR.SCL I/O SmartReflex I2C data I2C.CNTL.SDA I/O D4 I2C.CNTL.SDA I/O PU N/A GP I2C data I2C I2C.CNTL.SCL I/O D5 I2C.CNTL.SCL I/O PU N/A GP I2C clock PCM.VCK Data clock (voice port) I/O R1 PCM.VCK I/O Floating PCM.VDR Data receive (voice port) I/O T2 PCM.VDR I/O GND PCM PCM.VDX Data transmit (voice port) I/O T15 PCM.VDX I/O Floating PCM.VFS Frame synchronization (voice port) I/O R16 PCM.VFS I/O Floating I2S.CLK Clock signal (audio port) I/O L3 I2S.CLK I/O Floating I2S.SYNC Synchronization signal (audio port) I/O K6 I2S.SYNC I/O Floating TDM I2S.DIN Data receive (audio port) I K4 I2S.DIN I GND I2S.DOUT Data transmit (audio port) O K3 I2S.DOUT O Floating MIC.MAIN.P Main microphone left input (P) I E2 MIC.MAIN.P I Cap to GND MIC.MAIN.M Main microphone left input (M) I F2 MIC.MAIN.M I Cap to GND MIC.SUB.P Main microphone right input (P) I ANA.MIC G2 MIC.SUB.P I Cap to GND DIG.MIC.0 Digital microphone 0 input data I MIC.SUB.M Main microphone right input (M) I H2 MIC.SUB.M I Cap to GND DIG.MIC.1 Digital microphone 1 input data I HSMIC.P Headset microphone input (P) I E3 HSMIC.P I Cap to GND Headset microphone HSMIC.M Headset microphone input (M) I F3 HSMIC.M I Cap to GND Copyright © 2008–2011, Texas Instruments Incorporated Terminal Description 21 Submit Documentation Feedback Product Folder Link(s): TPS65950 |
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