TTP-C2NF Communication Controller – Data Sheet

AS8202NF

Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.

9

TXD[1,0], CTS[1,0],

LED[2:0], INTB

Transition Time – Fall

Tf

T(Vout=0.9*VDD)

to

T(Vout=0.1*VDD)

T = 125 °C,

Slow Process,

VDD=3.0V,

Cload=35pF

D[15:0], READYB

ns

Note 1: If Min/Max values are both negative, they are ordered according to their absolute value.

Note 2: Typical value, not tested during production.

Note 3: Implicitly tested.

8 . Ap p l i c a t i o n I n f o r m a t i o n

8.1.

Host CPU Interface

The host CPU interface, also referred to as CNI (Communication Network Interface), connects

the application circuitry to the AS8202NF TTP controller. All related signal pins provide an

asynchronous read/write access to a dual ported RAM located in the AS8202NF. There are no

setup/hold constraints referring to the microtick (main clock “CLK0”).

All accesses have to be executed on a granularity of 16 bit (2 byte), the device does not

support byte-wide accesses. Pin A0 (LSB) of the device differentiates even and odd 16 bit word

addresses and is typically connected to A1 of a little-endian host CPU. A0 of the host CPU is

not connected to the device, and the application/driver on the host CPU should force all

accesses to be 16 bit. For efficiency reasons, the host CPU appliation/driver may access some

memory locations of the AS8202NF using wider accesses (e.g. 32 bit), and the bus interface of

the host CPU will automatically split the access into two consecutive 16-bit wide accesses to

the TTP controller. Note that particularly in such a setup all timing parameters of the host CPU

interface must be met, especially the inactivity timeouts described as symbols 16–19.

The host interface features an interrupt or time signal INTB to notify the application circuitry of

programmed and protocol-specific, synchronous and asynchronous events.

The host CPU interface allows access to the internal instruction code memory. This is required

for proper loading of the protocol execution code into the internal instruction code RAM, for

extensive testing of the instruction code RAM and for verifying the instruction code ROM

contents.

INTB is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any

other time, so external pull-up resistors or transistors may be necessary depending on the

application.

READYB is also an open-drain output, but with a possibility to be driven to ‘1’ for a defined time

(selectable by register) before weak-pull-up at any other time.

The LED port is software-configurable to automatically show some protocol-related states and

events, see below for the LED port configuration.

Host Interface Ports

Pin Name

Mode

Width

Comment

A[11:0]

in

12

CNI address bus, 12 bit (A0 is LSB)

D[15:0]

inout (tri)

16

CNI data bus, 16 bit (D0 is LSB)

CEB

in

1

CNI chip enable, active low

WEB

in

1

CNI write enable, active low

OEB

In

1

CNI output enable, active low

READYB

out (open drain)

1

CNI ready, active low