TTP-C2NF Communication Controller – Data Sheet

AS8202NF

Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.

16

and to be gluelessly compatible with the commercial 100 Mbit/s Ethernet MII (Media

Independent Interface) according to IEEE standard 802.3 (Ethernet CSMA/CD).

Connecting the synchronous TTP bus unit to a 100 Mbit/s Ethernet PHY is done by connecting

TXD, CTS, TXCLK, RXER, RXCLK, RXDV and RXD of any channel to TXD0, TXEN, TXCLK,

RXER, RXCLK, RXDV and RXD0 of the PHY's MII. The pins TXD1, TXD2 and TXD3 of the

PHY's MII should be linked to VSS. The signals RXD1, RXD2, RXD3, COL and CRS as well as

the MMII (Management Interface) should be left open or can be used for diagnostic purposes

by the application.

Note that the frames sent by the AS8202NF are not Ethernet compatible and that an Ethernet

Hub (not a Switch) can be used as a 'star coupler' for proper operation. Also note that the

Ethernet PHY must be configured for Full Duplex operation (even though the Hub does not

support full duplex), because TTP has its own collision management that should not interfere

with the PHY's Half-Duplex collision management. In general, the PHY must not be configured

for automatic configuration ('Auto negotiation') but be hard-configured for 100 Mbit/s, Full

Duplex operation. Note that to run the interface at a rate other than 25 Mbit/s other transceiver

PHY components have to be used.

Pin Name

Mode

Connect to PHY

Comment

TXD[0]

out

TXD0

Transmit data channel 0

CTS[0]

out

TXEN

Transmit enable channel 0

TXCLK[0]

in

TXCLK

Transmit clock channel 0

RXER[0]

in

RXER

Receive error channel 0

RXCLK[0]

in

RXCLK

Receive clock channel 0

RXDV[0]

in

RXDV

Receive data valid channel 0

RXD[0]

in

RXD0

Receive data channel 0

TXD[1]

out

TXD0

Transmit data channel 1

CTS[1]

out

TXEN

Transmit enable channel 1

TXCLK[1]

in

TXCLK

Transmit clock channel 1

RXER[1]

in

RXER

Receive error channel 1

RXCLK[1]

in

RXCLK

Receive clock channel 1

RXDV[1]

in

RXDV

Receive data valid channel 1

RXD[1]

in

RXD0

Receive data channel 1

8.6.

Test Interface

The Test Interface supports the manufacturing test and characterization of the chip. In the

application environment test pins have to be connected as following:

STEST, FTEST, FIDIS: connect to VSS

TTEST: connect to VDD

Warning: Any other connection of these pins may cause permanent damage to

the device and to additional devices of the application.