TTP-C2NF Communication Controller – Data Sheet

AS8202NF

Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.

11

Asynchronous DPRAM interface

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Controller Cycle Time

Tc

25

ns

1a

A[11:0]

Input Valid to CEB, WEB (Setup Time)

2a

D[15:0]

5

ns

1b

A[11:0]

3

CEB, WEB to Input Invalid (Hold Time)

2b

D[15:0]

4

ns

Input Rising to CEB, WEB Falling

3

CEB, WEB, OEB

5

1,2

ns

CEB, WEB Rising to Input Falling

4

CEB, WEB, OEB

5

1,2

ns

Write Access Time (CEB, WEB to

READYB)

5

min = 1 Tc, max = 4 Tc

25

100

ns

CEB, WEB de-asserted to READYB de-

asserted

6

9.4

ns

Input Valid to CEB, OEB (Setup Time)

7a

A[11:0]

5

ns

CEB, OEB to Input Invalid (Hold Time)

7b

A[11:0]

2

ns

Input Rising to CEB, OEB Falling

8

CEB, WEB, OEB

5

1

ns

CEB, OEB Rising to Input Falling

9

CEB, WEB, OEB

5

1

ns

Read Access Time (CEB, OEB to

READYB)

10

min = 1.5 Tc, max = 8 Tc

37.5

200

ns

CEB, OEB asserted to signal asserted

11a

D[15:0]

4.0

8.4

ns

11b

D[15:0]

3.8

8

CEB, OEB de-asserted to signal de-

asserted

11c

READYB

8.8

ns

READYB, D skew

12

±2

ns

RAM_CLK_TESTSE Rising to READYB

Falling

13

USE_RAM_CLK='1'

3.7

13.5

ns

RAM_CLK_TESTSE Rising to READYB

Rising

14

USE_RAM_CLK='1'

3

9.7

ns

Ready delay='00'

3.6

12.9

Ready delay='01'

4.5

15.4

Ready delay='10'

5.4

18.8

RAM_CLK_TESTSE Rising to READYB

Deactivated 1->Z

15

USE_RAM_CLK

='1'

Ready delay='11'

6.4

22.2

ns

Read to Read Access Inactivity Time

(CEB, OEB low to CEB, OEB low)

16

min = 1.5 Tc

37.5

1

ns

Read to Write Access Inactivity Time

(CEB, OEB low to CEB, WEB low)

17

5

1

ns

Write to Write Access Inactivity Time

(CEB, WEB low to CEB, WEB low)

18

5

1,2

ns

Write to Read Access Inactivity Time

(CEB, WEB low to CEB, OEB low)

19

5

1,2

ns

Note 1: Prior to starting a read or write access, CEB, WEB and OEB have to be stable for at least 5 ns (see symbol 3, 4, 8, 9). In addition the designer

has to consider the minimum inactivity time according to symbols 16, 17, 18, 19. See Figure 3 for more information on the inactivity times.

Note 2: To allow proper internal initialization, after finishing any write access (CEB or WEB is high) to the internal CONTROLLER_ON register, CEB

OEB and WEB have to be stable high within 200 ns ( min = 8 Tc).

Note:

All values not tested during production, guaranteed by design.