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AS8506 Datasheet(PDF) 78 Page - ams AG

Part # AS8506
Description  Battery Cell Monitor and Balancer IC
PDF  89 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS8506 Datasheet(HTML) 78 Page - ams AG

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AS8506 – 78
ams Datasheet, Confidential:2013-Sep [1-00]
A p pl i c at io n I n f o r m at i o n
Figure 101:
Application with Opto-Coupler/ Isolation Device
Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the
battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing
the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery
pack from bottom will damage the system.
7
6
5
1
7
6
5
1
100nF
2-5uF
100nF
2-5uF
VSUP1
VSUP1
TU1
TU2
TU2
TU1
TL1
TL2
TL1
TL2
V5V
V5V_U
VSUP1
VSUP2
Micro
controller
CS
SCLK
SDI
SDO
TRIG
CLK
CVT_NOK
BD
WAKE
TSECL2
VSUP2
NTC
NTC
NTC
NTC
VSUP1
Note: If slave has to drive
FD pin then SDI has to be
connected local ground
Note: Open drain on WAKE_IN
pin in the µC or Transistor as
shown above.
VCELL3
VCELL2
SDO
CS
SCLK
SDI
34
33
32
40
39
38
37
36
35
17
18
19
11
12
13
14
15
16
V5V
VCELL7
VCELL6
VCELL5
VCELL1
C-GND
TSECH
TSECL
VREF_H
TEMP_IN1
CELL_THL
CELL_THU
TEMP_IN2
31
20
REF_T
VCELL4
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
VCELL3
VCELL2
SDO
CS
SCLK
SDI
34
33
32
40
39
38
37
36
35
17
18
19
11
12
13
14
15
16
V5V
VCELL7
VCELL6
VCELL5
VCELL1
C-GND
TSECH
TSECL
VREF_H
TEMP_IN1
CELL_THL
CELL_THU
TEMP_IN2
31
20
REF_T
VCELL4
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
AS8506
MLF 6x6
GND
(Exposed Pad)
AS8506
MLF 6x6
GND
(Exposed Pad)
Converter
for active
balancing
100 V device
Supply from Stack
TSECH1
TSECH2
TSECL2
100 mA load
FD_OUT2
Non-inverting
Optocoupler/
isolation device
7
6
5
1
7
6
5
1
100nF
2-5uF
100nF
2-5uF
VSUP1
VSUP1
TU1
TU2
TU2
TU1
TL1
TL2
TL1
TL2
V5V
V5V_U
VSUP1
VSUP2
Micro
controller
CS
SCLK
SDI
SDO
TRIG
CLK
CVT_NOK
BD
WAKE
TSECH1
TSECL1
TSECH2
VSUP2
NTC
NTC
NTC
NTC
VSUP1
Note: If slave has to drive
FD pin then SDI has to be
connected local ground
Note: Open drain on WAKE_IN
pin in the µC or Transistor as
shown above.
VCELL3
VCELL2
SDO
CS
SCLK
SDI
34
33
32
40
39
38
37
36
35
17
18
19
11
12
13
14
15
16
V5V
VCELL7
VCELL6
VCELL5
VCELL1
C-GND
TSECH
TSECL
VREF_H
TEMP_IN1
CELL_THL
CELL_THU
TEMP_IN2
31
20
REF_T
VCELL4
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
VCELL3
VCELL2
SDO
CS
SCLK
SDI
34
33
32
40
39
38
37
36
35
17
18
19
11
12
13
14
15
16
V5V
VCELL7
VCELL6
VCELL5
VCELL1
C-GND
TSECH
TSECL
VREF_H
TEMP_IN1
CELL_THL
CELL_THU
TEMP_IN2
31
20
REF_T
VCELL4
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
AS8506
MLF 6x6
GND
(Exposed Pad)
AS8506
MLF 6x6
GND
(Exposed Pad)
100 mA load
Converter
for active
balancing
100 V device
Supply from Stack
TSECL1
TSECH2
TSECL2
100 mA load
100 V device
FD_OUT2
Non-inverting
Optocoupler/
isolation device
Optional Factory Setting for Active Balancing
CS
SCLK
SDI
SDO



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