DS2172

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BIT ERROR COUNT REGISTERS

(MSB)

(LSB)

BEC31

BEC30

BEC29

BEC28

BEC27

BEC26

BEC25

BEC24

BECR3

(addr.=0C Hex)

BEC23

BEC22

BEC21

BEC20

BEC19

BEC18

BEC17

BEC16

BECR2

(addr.=0D Hex)

BEC15

BEC14

BEC13

BEC12

BEC11

BEC10

BEC9

BEC8

BECR1

(addr.=0E Hex)

BEC7

BEC6

BEC5

BEC4

BEC3

BEC2

BEC1

BEC0

BECR0

(addr.=0F Hex)

10.0 PATTERN RECEIVE REGISTERS

The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The

operation of these registers depends on the synchronization status of the DS2172. Asserting the RL bit

(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received

at RDATA into the PRR registers. When the DS2172 is in sync (SR.0 = 1) asserting RL will latch the

pattern that to which the device has established synchronization. Since the receiver has no knowledge of

the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an

example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,

11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the

PRR registers.

PATTERN RECEIVE REGISTERS

(MSB)

(LSB)

PR31

PR30

PR29

PR28

PR27

PR26

PR25

PR24

PRR3 (addr.=10 Hex)

PR23

PR22

PR21

PR20

PR19

PR18

PR17

PR16

PRR2 (addr.=11 Hex)

PR15

PR14

PR13

PR12

PR11

PR10

PR9

PR8

PRR1 (addr.=12 Hex)

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

PRR0 (addr.=13 Hex)

11.0 STATUS REGISTER AND INTERRUPT MASK REGISTER

The Status Register (SR) contains information on the current real time status of the DS2172. When a

particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these

registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a

bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,

and BECOF status bits, they will be cleared when read and will not be set again until the event has

occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no

longer persists.

and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask

Register (IMR).