* This specification is subject to be changed without notice.

4.17.2000

EM78P860

8 -BIT MICRO-CONTROLLER

7

Fig. 6 The relation between /LPD,/POVD

• Bit6(read/write)(PLL enable signal)

0/1=DISABLE/ENABLE

The relation between 32.768K and 3.679M can see Fig. 7.

Fig. 7 The relation between 32.768K and 3.679K .

• Bit7 IDLE: sleep mode selection bit

0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go.

These IDLE mode can be waken up by TCC clock or Watch Dog or PORT9 and run from “SLEP” next instruction.

These SLEEP mode can be waken up by Watch Dog or PORT9 and run from address “00”.

SLEEP mode

IDLE mode

GREEN mode

NORMAL mode

RA(7,6)=(0,0)

RA(7,6)=(1,0)

RA(7,6)=(x,0)

RA(7,6)=(x,1)

+ SLEP

+ SLEP

no SLEP

no SLEP

TCC time out

X

Wake-up

Interrupt

Interrupt

+ Interrupt

+ Next instruction

WDT time out

RESET

Wake-up

RESET

RESET

+ Next instruction

RESET

RESET

Port9 wake-up

RESET

Wake-up

+ Next instruction

• Bit4(Read Only)(Low battery signal) 0/1 = Battery voltage is low/Normal .

If the battery voltage is under 3.6V then sends a ‘0’ signal to RA register bit4 or a ‘1’ signal to this Bit if VDD

is over 3.8V.

• Bit5(read/Write)(Low battery detect enable)

0/1 = low battery detect DISABLE/ENABLE.

The relation between /LPD,/POVD and /LOW_BAT can see Fig 6.

Vdd

Vref

s2

1 on

0 off

s2

1 on

0 off

1 on

to Low bat

To rese

t

/POVD

/LPD

/LPD

+

-

1 on

32.768K

PLL

3.679M

/358E

switch

To system clock

0

1