* This specification is subject to be changed without notice.

4.17.2000

EM78P860

8 -BIT MICRO-CONTROLLER

13

VII.3 TCC/WDT Prescaler

There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or

WDT only at the same time.

• An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT

register.

• See the prescaler ratio in CONT register.

• Fig. 10 depicts the circuit diagram of TCC/WDT.

• Both TCC and prescaler will be cleared by instructions which write to TCC each time.

• The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.

• The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.

WDTE

WDT timeout

PAB

PAB

MUX

8-to-1 MUX

PSR0~PSR2

8-bit Counter

M

U

X

0

1

WDT

PAB

TCC overflow interrupt

Data Bus

TCC(R1)

SYNC

2 cycle

M

U

X

M

U

X

1

0

0

1

TE

TS

TCC

(32K CLK)

CLK(=Fosc/2)

Fig. 10 Block diagram of TCC WDT

VII.4

I/O Ports

The I/O registers, Port 6 ~ Port 9, are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by software

control. The I/O ports can be defined as “input” or “output” pins by the I/O control registers (IOC6 ~ IOC9 ) under

program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is

shown in Fig. 11.