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LP3907 Datasheet(PDF) 27 Page - Texas Instruments |
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LP3907 Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 57 page ![]() EN1 nPOR RDY1 EN2 RDY2 EN1 nPOR RDY1 EN2 RDY2 0V 0V Case1 Case2 EN1 nPOR RDY1 EN2 RDY2 Case3 Counter delay t1 t2 t1 t2 Counter delay t1 t2 Counter delay LP3907 www.ti.com SNVS511N – JUNE 2007 – REVISED AUGUST 2011 Figure 7. NPOR With Counter Delay The above diagram shows the simplest application of the Power On Reset, where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR will stay LOW, indicating a power fail mode. Case 2 indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW. Case 3 shows a typical application of the Power On Reset, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal will trigger a programmable delay before going HIGH, as explained below. Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LP3907 |
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