LP3907 datasheet(29/57 Pages) TI1

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RDY1

RDY2

Counter

delay

EN1

EN2

nPOR

Counter

delay

nPOR

Mask Time

Counter

delay

Case 2:

Case 1:

Mask

Window

Mask

Window

RDY2

EN2

nPOR

Mask Time

LP3907

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SNVS511N – JUNE 2007 – REVISED AUGUST 2011

Figure 9. NPOR Mask Window

If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted as explained

above.

In Case 1, we see that case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent

the nPOR being asserted again, a masked window ( 5ms ) counter delay is triggered off the EN2 rising edge.

nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards will depend on the

status of both RDY1 and RDY2 lines.

In Case 2, we see the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2

never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and

RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW

after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

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