LP3907 datasheet(44/57 Pages) TI1

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LP3907

SNVS511N – JUNE 2007 – REVISED AUGUST 2011

www.ti.com

Capacitor

Min Value

Unit

Description

Recommended Type

CLDO1

0.47

µF

LDO1 output capacitor

Ceramic, 6.3V, X5R

CLDO2

0.47

µF

LDO2 output capacitor

Ceramic, 6.3V, X5R

CSW1

10.0

µF

SW1 output capacitor

Ceramic, 6.3V, X5R

CSW2

10.0

µF

SW2 output capacitor

Ceramic, 6.3V, X5R

I2C Pullup Resistor

Both SDA and SCL terminals need to have pullup resistors connected to VINLDO12 or to the power supply of the

I2C master. The values of the pull-up resistors (typ.

∼1.8kΩ) are determined by the capacitance of the bus. Too

large of a resistor combined with a given bus capacitance will result in a rise time that would violate the max. rise

time specification. A too small resistor will result in a contention with the pull-down transistor on either slave(s) or

master.

Operation without I2C Interface

Operation of the LP3907 without the I2C interface is possible if the system can operate with default values for the

LDO and Buck regulators. (Read below: Factory programmable options). The I2C-less system must rely on the

correct default output values of the LDO and Buck converters.

Factory Programmable Options

The following options are EPROM programmed during final test of the LP3907. The system designer that needs

specific options is advised to contact the local National Semiconductor sales office.

Factory programmable options

Current value

Enable delay for power on

code 010 (see Control 1 register section)

SW1 ramp speed

8 mV/µs

SW2 ramp speed

8 mV/µs

The I2C Chip ID address is offered as a metal mask option. The current address for the LLP chip equals 0x60,

while the address for the micro SMD chip is 0x61.

HIGH VIN HIGH-LOAD OPERATION

Additional information is provided when the IC is operated at extremes of VIN and regulator loads. These are

described in terms of the Junction temperature and, Buck output ripple management.

JUNCTION TEMPERATURE

The maximum junction temperature TJ-MAX-OP of 125°C of the IC package.

The following equations demonstrate junction temperature determination, ambient temperature TA-MAX and Total

chip power must be controlled to keep TJ below this maximum:

TJ-MAX-OP = TA-MAX + (θJA) [°C/ Watt] * (PD-MAX) [Watts]

Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor

amount for chip overhead. Chip overhead is Bias, TSD & LDO analog.

PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A * VIN) [Watts].

Power dissipation of LDO1

PLDO1 = (VINLDO1- VOUTLDO1) * IoutLDO1 [V*A]

Power dissipation of LDO2

PLDO2 = (VINLDO2 - VoutLDO2) * IoutLDO2 [V*A]

Power dissipation of Buck1

PBuck1 = PIN – POUT =

VoutBuck1* IoutBuck1 * (1 -η1) / η1 [V*A]

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