LP3907 datasheet(28/57 Pages) TI1

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EN1

nPOR

RDY1

EN2

RDY2

Counter

delay

Counter

delay

LP3907

SNVS511N – JUNE 2007 – REVISED AUGUST 2011

www.ti.com

Figure 8. Faults Occurring in Counter Delay After Startup

The above timing diagram details the Power good with delay with respect to the enable signals EN1, and EN2.

The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been

trimmed as follows:

Comparator Level

Buck Supply Level

HIGH

Greater than 94%

LOW

Less than 85%

The circuits for EN1 and RDY1 is symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also

work for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay

counter (50

μs, 50ms, 100ms, 200ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is

then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this

interval the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

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