LP3907 datasheet(30/57 Pages) TI1

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Delay Mask Counter

Delay

nPOR

EN1

RDY1

EN2

RDY2

POR

LP3907

SNVS511N – JUNE 2007 – REVISED AUGUST 2011

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Figure 10. Design Implementation of the Flexible Power-On Reset

An internal Power-on reset of the IC is used with EN1, and EN2 to produce a reset signal (LOW) to the delay

timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer.

S=R=1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to

generate outputs to the final AND gate to generate the nPOR.

Under Voltage Lock Out

The LP3907 features an “under voltage lock out circuit”. The function of this circuit is to continuously monitor the

raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply

voltage is less than 2.8VDC.

The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8VDC

trip point for a VIN OK – Not OK detector. This VIN OK signal is then used to gate the enable signals to the four

regulators of the LP3907. When VINLDO12 is greater than 2.8VDC the four enables control the four regulators,

when VINLDO12 is less than 2.8VDC the four regulators are disabled by the VIN detector being in the “Not OK”

state. The circuit has built in hysteresis to prevent chattering occurring.

2C Compatible Serial Interface

I2C SIGNALS

The LP3907 features an I2C compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock

and data respectively. Both signals need a pull-up resistor according to the I2C specification. The LP3907

interface is an I2C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400kbit/s. See I2C

specification from Philips for further details.

I2C DATA VALIDITY

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the

data line can only be changed when CLK is LOW.

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