LM2633

SNVS139C – MAY 2004 – REVISED APRIL 2005

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is adjustable. The two switching controllers have under-voltage and over-voltage latch protections, and the linear

regulator has under-voltage latch protection. Under-voltage latch can be disabled or delayed by a programmable

amount of time.

The input voltage for the switching channels ranges from 5V to 30V, which makes possible the choice of different

battery chemistries and options.

Connection Diagram

TOP VIEW

Figure 1. 48-Lead TSSOP (MTD)

Pin Functions

Pin Descriptions

FB1 (Pin 1):The feedback input for Channel 1. Connect to the load directly.

COMP1 (Pin 2): Channel 1 compensation network connection (connected to the output of the voltage error amplifier).

NC (Pins 3, 14, 15, 20, 26, 28, 37 and 47): No internal connection.

ON/SS1 (Pin 4): Adding a capacitor to this pin provides a soft-start function which minimizes inrush current and output voltage overshoot; A

lower than 0.8V input (open-collector type) at this pin turns off Channel 1; also if both ON/SS1 and ON/SS2 pins are below 0.8V, the whole

ON/SS2 (Pin 5): Adding a capacitor to this pin provides a soft-start function which minimizes inrush current and output voltage overshoot; A

lower than 0.8V input (open-collector type) at this pin turns off Channel 2; also if both ON/SS1 and ON/SS2 pins are below 0.8V, the whole

VID4-0 (Pins 6-10): Voltage identification code. Each pin has an internal pull-up. They can accept open collector compatible 5-bit binary

code from the CPU. The code table is shown in Table 3.

UV_ DELAY (Pin 11): A capacitor from this pin to ground adjusts the delay for the output under-voltage lockout.

FPWM (Pin 12): When FPWM is low, pulse-skip mode operation at light load is disabled. The regulator is forced to operate in constant

frequency mode.

2

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