LM2633

www.ti.com

SNVS139C – MAY 2004 – REVISED APRIL 2005

Table 2. POWER GOOD TRUTH TABLE (continued)

Input

Output

ovp1

ovp2

uvpg1

uvpg2

uvpglr

new vid

ch1 on

ch2 on

fault

latch off

PGOOD

1

0

π = 0

0

1

0

1

0

All other combinations

1

Table 3. VID CODE AND DAC OUTPUT

VID4

VID3

VID2

VID1

VID0

DAC Voltage (V)

1

1

1

1

1

No CPU*

1

1

1

1

0

0.925

1

1

1

0

1

0.950

1

1

1

0

0

0.975

1

1

0

1

1

1.000

1

1

0

1

0

1.025

1

1

0

0

1

1.050

1

1

0

0

0

1.075

1

0

1

1

1

1.100

1

0

1

1

0

1.125

1

0

1

0

1

1.150

1

0

1

0

0

1.175

1

0

0

1

1

1.200

1

0

0

1

0

1.225

1

0

0

0

1

1.250

1

0

0

0

0

1.275

0

1

1

1

1

No CPU

0

1

1

1

0

1.30

0

1

1

0

1

1.35

0

1

1

0

0

1.40

0

1

0

1

1

1.45

0

1

0

1

0

1.50

0

1

0

0

1

1.55

0

1

0

0

0

1.60

0

0

1

1

1

1.65

0

0

1

1

0

1.70

0

0

1

0

1

1.75

0

0

1

0

0

1.80

0

0

0

1

1

1.85

0

0

0

1

0

1.90

0

0

0

0

1

1.95

0

0

0

0

0

2.00

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2004–2005, Texas Instruments Incorporated

Submit Documentation Feedback

7

Product Folder Links: LM2633