LM2633 datasheet(21/47 Pages) TI1

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LM2633

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SNVS139C – MAY 2004 – REVISED APRIL 2005

causing the output voltage to ramp up. During this time, the error amplifier output voltage is clamped at 0.8V, and

the duty cycle generated by the PWM comparator is ignored. When the corresponding output voltage exceeds

99% of the set target voltage, the mode of the channel transitions from soft start to operating. As a result, the

high clamp at the output of the error amplifier is switched to 2V. Beyond this point, once the PWM pulses

generated by the PWM comparator are wider than that generated by the MIN_ON_TIME comparator, the PWM

comparator takes over and starts to regulate the output voltage. That is, peak current mode control now takes

place.

The speed at which the duty cycle grows depends on the capacitance of the soft start capacitor. The higher the

capacitance, the slower the speed. However, that speed is independent of how fast the input voltage rises. That

is because the ramp signal used to generate the soft start duty cycle has a slope proportional to input voltage,

making the product of duty cycle and input voltage a value that is independent of input voltage. This feature

makes the soft start process more predictable and reliable because whether the input power supply goes through

a soft start process or is applied abruptly does not affect the LM2633 soft start.

During soft start, under-voltage protection is disabled. But over-voltage protection and current limit are in place.

When the ON/SSx pin voltage exceeds 3.5V, a soft start time out signal (sstox) will be issued. This signal

enables the under-voltage protection. See the Under-Voltage Protection section.

SHUTDOWN MODE

If both ON/SSx pins are pulled low, the IC will be in shut down mode. Both top gate-drives of the two switching

channels are turned off while both bottom gate-drives remain on. The linear channel is also disabled.

The same thing happens to the gate drives when the input voltage is brought below the UVLO threshold.

TURNING OFF A SWITCHING CHANNEL

A switching channel can be turned off by pulling its ON/SSx pin below about 1.1V. Upon detecting a low level on

ON/SSx pin, the corresponding top gate-drive will be turned off and the bottom gate-drive will be turned on.

In a high current application, it may be necessary to take special measures to make sure that the output voltage

does not go too negative during shutdown. One of those measures is to add a Schottky diode in parallel with

output capacitors. Another measure is to fine tune the power stage parameters such as inductance and

capacitance values.

FAULT STATE

Whenever the input voltage becomes too low (less than about 3.9V), or the IC is too hot and enters thermal shut

down mode, a "fault" signal will be generated internally. This signal will discharge the capacitor connected

between the ON/SSx pin and ground with 3 µA of current until the pin reaches 1.1V. The switching channels will

be turned off upon seeing this signal.

In the fault state, OVP and UVP are disabled and shut down latch is released.

FORCE-PWM MODE

This mode applies to both switching channels si-multaneously. The force-PWM mode is activated by pulling the

FPWM pin to logic low. In this mode, the top FET and the bottom FET gate signals are always complementary to

each other. The 0-CROSSING / NEGATIVE CURRENT LIMIT comparator will be set to detect the negative

current limit. In force-PWM mode, the regulator always operates in Continuous Conduction Mode (CCM) and its

steady-state duty cycle (approximately VOUT / VIN) is almost independent of load.

The force-PWM mode is good for applications where fixed switching frequency is required. It also offers the

fastest load transient response.

In force-PWM mode, the top FET has to be turned on for a minimum of 220ns each cycle. However, when the

required duty cycle is less than the minimum value, the skip comparator will be activated and pulses will be

skipped to maintain regulation.

SKIP COMPARATOR

Whenever the COMPx pin voltage goes below the 0.5V threshold, the PWM cycles will be "skipped" until that

voltage again exceeds the threshold.

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