28F008SA datasheet(9/33 Pages) INTEL

9 / 33 page

28F008SA

PRINCIPLES OF OPERATION

The 28F008SA includes on-chip write automation to

manage write and erase functions The Write State

Machine allows for 100% TTL-level control inputs

fixed power supplies during block erasure and byte

write and minimal processor overhead with RAM-

like interface timings

After initial device powerup or after return from

deep powerdown mode (see Bus Operations) the

28F008SA functions as a read-only memory Manip-

ulation of external memory-control pins allow array

read standby and output disable operations Both

Status Register and intelligent identifiers can also be

accessed through the Command User Interface

when VPP e VPPL

This same subset of operations is also available

when high voltage is applied to the VPP pin In addi-

tion high voltage on VPP enables successful block

erasure and byte writing of the device All functions

associated with altering memory contentsbyte

write block erase status and intelligent identifier

are accessed via the Command User Interface and

verified thru the Status Register

Commands are written using standard microproces-

sor write timings Command User Interface contents

serve as input to the WSM which controls the block

erase and byte write circuitry Write cycles also inter-

nally latch addresses and data needed for byte write

or block erase operations With the appropriate com-

mand written to the register standard microproces-

sor read timings output array data access the intelli-

gent identifier codes or output byte write and block

erase status for verification

Interface software to initiate and poll progress of in-

ternal byte write and block erase can be stored in

any of the 28F008SA blocks This code is copied to

and executed from system RAM during actual flash

memory update After successful completion of byte

write andor block erase codedata reads from the

28F008SA are again possible via the Read Array

command Erase suspendresume capability allows

system software to suspend block erase to read

data and execute code from any other block

FFFFF

64-Kbyte Block

EFFFF

F0000

64-Kbyte Block

DFFFF

E0000

64-Kbyte Block

CFFFF

D0000

64-Kbyte Block

BFFFF

C0000

64-Kbyte Block

AFFFF

B0000

64-Kbyte Block

9FFFF

A0000

64-Kbyte Block

8FFFF

90000

64-Kbyte Block

7FFFF

80000

64-Kbyte Block

6FFFF

70000

64-Kbyte Block

5FFFF

60000

64-Kbyte Block

4FFFF

50000

64-Kbyte Block

3FFFF

40000

64-Kbyte Block

2FFFF

30000

64-Kbyte Block

1FFFF

20000

64-Kbyte Block

0FFFF

10000

64-Kbyte Block

00000

Figure 6 Memory Map

Command User Interface and Write

Automation

An on-chip state machine controls block erase and

byte write freeing the system processor for other

tasks After receiving the Erase Setup and Erase

Confirm commands

the state machine controls

block pre-conditioning and erase returning progress

via the Status Register and RYBY

output Byte

write is similarly controlled after destination address

and expected data are supplied The program and

erase algorithms of past Intel flash memories are

now regulated by the state machine including pulse

repetition where required and internal verification

and margining of data

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