28F008SA datasheet(15/33 Pages) INTEL

15 / 33 page

28F008SA

RYBY

and Byte WriteBlock Erase

Polling

RYBY

is a full CMOS output that provides a hard-

ware method of detecting byte write and block erase

completion It transitions low time tWHRL after a

write or erase command sequence is written to the

28F008SA and returns to VOH when the WSM has

finished executing the internal algorithm

RYBY

can be connected to the interrupt input of

the system CPU or controller It is active at all times

not tristated if the 28F008SA CE

or OE

inputs

are brought to VIH RYBY

is also VOH when the

device is in Erase Suspend or deep powerdown

modes

290429 – 6

Bus

Command

Comments

Operation

Write

Byte Write

Data e 40H (10H)

Setup

Address e Byte to be written

Write

Byte Write

Data to be written

Address e Byte to be written

StandbyRead

Check RYBY

VOH e Ready VOL e Busy

Read Status Register

Check SR7

1 e Ready 0 e Busy

Toggle OE

or CE

update Status Register

Repeat for subsequent bytes

Full status check can be done after each byte or after a

sequence of bytes

Write FFH after the last byte write operation to reset the

device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

290429 – 7

Bus

Command

Comments

Operation

Optional

CPU may already have read

Status Register data in WSM

Read

Ready polling above

Standby

Check SR3

1 e VPP Low Detect

Standby

Check SR4

1 e Byte Write Error

SR3 MUST be cleared if set during a byte write attempt

before further attempts are allowed by the Write State

Machine

SR4 is only cleared by the Clear Status Register Command

in cases where multiple bytes are written before full status is

checked

If error is detected clear the Status Register before

attempting retry or other error recovery

Figure 7 Automated Byte Write Flowchart

28F008SA Datasheet(PDF) 15 Page - Intel Corporation

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