28F008SA datasheet(14/33 Pages) INTEL

14 / 33 page

28F008SA

Byte Write SetupWrite Commands

(40H or 10H)

Byte write is executed by a two-command sequence

The Byte Write Setup command (40H or 10H) is writ-

ten to the Command User Interface followed by a

second write specifying the address and data

(latched on the rising edge of WE ) to be written

The WSM then takes over controlling the byte write

and write verify algorithms internally After the two-

command byte write sequence is written to it the

28F008SA automatically outputs Status Register

data when read (see Figure 7 Byte Write Flowchart)

The CPU can detect the completion of the byte write

event by analyzing the output of the RYBY

pin or

the WSM Status bit of the Status Register Only the

Read Status Register command is valid while byte

write is active

When byte write is complete the Byte Write Status

bit should be checked If byte write error is detected

the Status Register should be cleared The internal

WSM verify only detects errors for ‘‘1’’s that do not

successfully write to ‘‘0’’s The Command User In-

terface remains in Read Status Register mode until

further commands are issued to it If byte write is

attempted while VPP e VPPL the VPP Status bit will

be set to ‘‘1’’ Byte write attempts while VPPL k VPP

VPPH produce spurious results and should not be

attempted

EXTENDED BLOCK ERASEBYTE

WRITE CYCLING

Intel has designed extended cycling capability into

its

ETOX

flash

memory

technologies

The

28F008SA is designed for 100000 byte writeblock

erase cycles on each of the sixteen 64-Kbyte

blocks Low electric fields advanced oxides and

minimal oxide area per cell subjected to the tunnel-

ing electric field combine to greatly reduce oxide

stress and the probability of failure A 20-Mbyte sol-

id-state drive using an array of 28F008SAs has a

MTBF (Mean Time Between Failure) of 333 million

hours(1) over 600 times more reliable than equiva-

lent rotating disk technology

AUTOMATED BYTE WRITE

The 28F008SA integrates the Quick-Pulse program-

ming algorithm of prior Intel Flash devices on-chip

using the Command User Interface Status Register

and Write State Machine (WSM) On-chip integration

dramatically simplifies system software and provides

processor interface timings to the Command User

Interface and Status Register WSM operation inter-

nal verify and VPP high voltage presence are moni-

tored and reported via the RYBY

output and ap-

propriate Status Register bits Figure 7 shows a

system software flowchart for device byte write The

entire sequence is performed with VPP at VPPH Byte

write abort occurs when RP

transitions to VIL or

VPP drops to VPPL Although the WSM is halted

byte data is partially written at the location where

byte write was aborted Block erasure or a repeat of

byte write is required to initialize this data to a

known value

AUTOMATED BLOCK ERASE

As above the Quick-Erase algorithm of prior Intel

Flash devices is now implemented internally includ-

ing all preconditioning of block data WSM opera-

tion erase success and VPP high voltage presence

are monitored and reported through RYBY

and

the Status Register Additionally if a command other

than Erase Confirm is written to the device following

Erase Setup both the Erase Status and Byte Write

Status bits will be set to ‘‘1’’s When issuing the

Erase Setup and Erase Confirm commands they

should be written to an address within the address

range of the block to be erased Figure 8 shows a

system software flowchart for block erase

Erase typically takes 16 seconds per block The

Erase SuspendErase Resume command sequence

allows suspension of this erase operation to read

data from a block other than that in which erase is

being performed A system software flowchart is

shown in Figure 9

The entire sequence is performed with VPP at VPPH

Abort occurs when RP

transitions to VIL or VPP

falls to VPPL while erase is in progress Block data is

partially erased by this operation and a repeat of

erase is required to obtain a fully erased block

DESIGN CONSIDERATIONS

Three-Line Output Control

The 28F008SA will often be used in large memory

arrays Intel provides three control inputs to accom-

modate multiple memory connections Three-line

control provides for

a) lowest possible memory power dissipation

b) complete assurance that data bus contention will

not occur

To efficiently use these control inputs an address

decoder should enable CE

while OE

should be

connected to all memory devices and the system’s

READ

control line This assures that only selected

memory devices have active outputs while deselect-

ed memory devices are in Standby Mode RP

should be connected to the system Powergood sig-

nal to prevent unintended writes during system pow-

er transitions Powergood should also toggle during

system reset

(1)Assumptions 10-Kbyte file written every 10 minutes (20-Mbyte array)(10-Kbyte file) e 2000 file writes before erase required

(2000 files writeserase) c (100000 cycles per 28F008SA block) e 200 million file writes

(200 c 106 file writes) c (10 minwrite) c (1 hr60 min) e 333 c 106 MTBF

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