28F008SA datasheet(23/33 Pages) INTEL

23 / 33 page

28F008SA

AC INPUTOUTPUT REFERENCE WAVEFORM(1)

290429 – 11

AC test inputs are driven at VOH (24 VTTL) for a Logic ‘‘1’’ and VOL (045 VTTL) for a Logic

‘‘0’’ Input timing begins at VIH (20 VTTL) and VIL (08 VTTL) Output timing ends at VIH and

VIL Input rise and fall times (10% to 90%) k 10 ns

AC TESTING LOAD CIRCUIT(1)

CL e 100 pF

CL Includes Jig

Capacitance

290429 – 12

RL e 33 kX

HIGH SPEED

AC INPUTOUTPUT REFERENCE WAVEFORM(2)

290429 – 17

AC test inputs are driven at 30V for a Logic ‘‘1’’ and 00V for a Logic ‘‘0’’ Input timing

begins and output timing ends at 15V Input rise and fall times (10% to 90%) k 10 ns

HIGH SPEED

AC TESTING LOAD CIRCUIT(2)

CL e 30 pF

CL Includes Jig

Capacitance

290429 – 18

RL e 33 kX

NOTES

1 Testing characteristics for 28F008SA-85 in Standard configuration and 28F008SA-120

2 Testing characteristics for 28F008SA-85 in High Speed configuration

AC CHARACTERISTICSRead-Only Operations(1)

Versions

VCCg5%

28F008SA-85(4)

Unit

VCCg10%

28F008SA-85(5)

28F008SA-120(5)

Symbol

Parameter

Notes

Min

Max

Min

Max

Min

Max

tAVAV

tRC

Read Cycle Time

120

tAVQV

tACC

Address to Output Delay

120

tELQV

tCE

to Output Delay

120

tPHQV

tPWH

High to Output Delay

400

tGLQV

tOE

to Output Delay

tELQX

tLZ

to Output Low Z

tEHQZ

tHZ

High to Output High Z

tGLQX

tOLZ

to Output Low Z

tGHQZ

tDF

High to Output High Z

tOH

Output Hold from

Addresses CE

or OE

Change Whichever is First

NOTES

1 See AC InputOutput Reference Waveform for timing measurements

2 OE

may be delayed up to tCE–tOE after the falling edge of CE

without impact on tCE

3 Sampled not 100% tested

4 See High Speed AC InputOutput Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris-

tics

5 See AC InputOutput Reference Waveforms and AC Testing Load Circuits for testing characteristics

28F008SA Datasheet(PDF) 23 Page - Intel Corporation

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