AD5362 datasheet(21/29 Pages) AD

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AD5362/AD5363

Rev. A | Page 20 of 2

RESET FUNCTION

The reset function is initiated by the RESET pin. On the rising

edge of RESET, the AD5362/AD5363 state machine initiates a

reset sequence to reset the X, M, and C registers to their default

values. This sequence typically takes 300 μs, and the user should

not write to the part during this time. On power-up, it is recom-

mended that the user bring RESET high as soon as possible to

properly initialize the registers.

When the reset sequence is complete (and provided that CLR is

high), the DAC output is at a potential specified by the default

outputs remain at SIGGNDx until the X, M, or C register is

updated and LDAC is taken low. The AD5362/AD5363 can be

returned to the default state by pulsing RESET low for at least

30 ns. Note that, because the reset function is triggered by the

rising edge, bringing RESET low has no effect on the operation

of the AD5362/AD5363.

CLEAR FUNCTION

CLR is an active low input that should be high for normal

operation. The CLR pin has an internal 500 kΩ pull-down

resistor. When CLR is low, the input to each of the DAC output

buffer stages (VOUT0 to VOUT7) is switched to the externally

set potential on the relevant SIGGNDx pin. While CLR is low,

all LDAC pulses are ignored. When CLR is taken high again,

the DAC outputs return to their previous values. The contents

of the input registers and DAC Register 0 to DAC Register 7 are

not affected by taking CLR low. To prevent glitches appearing

on the outputs, CLR should be brought low whenever the

output span is adjusted by writing to the offset DAC.

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the

user writes new data to the corresponding X1, C, or M registers.

During the calculation of X2, the BUSY output goes low. While

BUSY is low, the user can continue writing new data to the X1,

M, or C registers (see the

section for

more details), but no DAC output updates can take place.

The BUSY pin is bidirectional and has a 50 kΩ internal pull-up

resistor. When multiple AD5362 or AD5363 devices are used in

one system, the BUSY pins can be tied together. This is useful

when it is required that no DAC in any device be updated until

all other DACs are ready. When each device has finished updat-

ing the X2 (A or B) registers, it releases the BUSY pin. If

another device has not finished updating its X2 registers, it

holds BUSY low, thus delaying the effect of LDAC going low.

The DAC outputs are updated by taking the LDAC input low. If

LDAC goes low while BUSY is active, the LDAC event is stored

and the DAC outputs are updated immediately after BUSY goes

high. A user can also hold the LDAC input permanently low. In

this case, the DAC outputs update immediately after BUSY goes

high. Whenever the A/B select registers are written to, BUSY

also goes low, for approximately 600 ns.

The AD5362/AD5363 have flexible addressing that allows

writing of data to a single channel, all channels in a group, or

all channels in the device. This means that one, two, four, or

eight DAC register values may need to be calculated and

updated. Because there is only one multiplier shared between

eight channels, this task must be done sequentially, so the

length of the BUSY pulse varies according to the number of

channels being updated.

Table 9. BUSY Pulse Widths

Action

BUSY Pulse Width1

Loading input, C, or M to 1 channel2

1.5 μs maximum

Loading input, C, or M to 2 channels

2.1 μs maximum

Loading input, C, or M to 8 channels

5.7 μs maximum

BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns.

2 A single channel update is typically 1 μs.

The AD5362/AD5363 contain an extra feature whereby a DAC

written to since the last time LDAC was brought low. Normally,

when LDAC is brought low, the DAC registers are filled with

the contents of the X2A or X2B registers, depending on the

setting of the A/B select registers. However, the AD5362/

AD5363 update the DAC register only if the X2A or X2B data

has changed, thereby removing unnecessary digital crosstalk.

BIN/2SCOMP PIN

The BIN/2SCOMP pin determines if the output data is presented

as offset binary or twos complement. If this pin is low, the data

is straight binary. If it is high, the data is twos complement. This

affects only the X, C, and offset DAC registers; the M register and

the control and command data are interpreted as straight binary.

TEMPERATURE SENSOR

The on-chip temperature sensor provides a voltage output

at the TEMP_OUT pin that is linearly proportional to the

Centigrade temperature scale. The typical accuracy of the

temperature sensor is +1°C at +25°C and ±5°C over the −40°C

to +85°C range. Its nominal output voltage is 1.46 V at 25°C,

varying at 4.4 mV/°C. Its low output impedance, low self-

heating, and linear output simplify interfacing to temperature

control circuitry and analog-to-digital converters.

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