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Data Sheet

AD5380

I2C SERIAL INTERFACE

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,

unless otherwise noted.

Table 5.

Parameter1, 2

Limit at TMIN, TMAX

Unit

Description

fSCL

400

kHz max

SCL clock frequency

2.5

µs min

SCL cycle time

0.6

µs min

tHIGH, SCL high time

1.3

µs min

tLOW, SCL low time

0.6

µs min

tHD,STA, start/repeated start condition hold time

100

ns min

tSU,DAT, data setup time

t63

0.9

µs max

tHD,DAT, data hold time

µs min

tHD,DAT, data hold time

0.6

µs min

tSU,STA, setup time for repeated start

0.6

µs min

tSU,STO, stop condition setup time

1.3

µs min

tBUF, bus free time between a STOP and a START condition

t10

300

ns max

tR, rise time of SCL and SDA when receiving

ns min

tR, rise time of SCL and SDA when receiving (CMOS compatible)

t11

300

ns max

tF, fall time of SDA when transmitting

ns min

tF, fall time of SDA when receiving (CMOS compatible)

300

ns max

tF, fall time of SCL and SDA when receiving

20 + 0.1Cb4

ns min

tF, fall time of SCL and SDA when transmitting

400

pF max

Capacitive load for each bus line

Guaranteed by design and characterization, not production tested.

See Figure 6.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of

SCL’s falling edge.

Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.

Figure 6. I2C Compatible Serial Interface Timing Diagram

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

t11

t10

SDA

SCL

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