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AD5380 Datasheet(PDF) 12 Page - Analog Devices |
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AD5380 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 40 page ![]() AD5380 Data Sheet PARALLEL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 6. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t0 4.5 ns min REG0, REG1, address to WR rising edge setup time t1 4.5 ns min REG0, REG1, address to WR rising edge hold time t2 20 ns min CS pulse width low t3 20 ns min WR pulse width low t4 0 ns min CS to WR falling edge setup time t5 0 ns min WR to CS rising edge hold time t6 4.5 ns min Data to WR rising edge setup time t7 4.5 ns min Data to WR rising edge hold time t8 20 ns min WR pulse width high t94 700 ns min Minimum WR cycle time (single-channel write) t10 30 ns max WR rising edge to BUSY falling edge t114 670 ns max BUSY pulse width low (single-channel update) t12 30 ns min WR rising edge to LDAC falling edge t13 20 ns min LDAC pulse width low t14 100/2000 ns min/max BUSY rising edge to DAC output response time t15 20 ns min LDAC rising edge to WR rising edge t16 0 ns min BUSY rising edge to LDAC falling edge t17 100/2000 ns min/max LDAC falling edge to DAC output response time t18 8 µs typ DAC output settling time t19 20 ns min CLR pulse width low t20 40 µs max CLR pulse activation time 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 7. 4 See Figure 29. Rev. D | Page 12 of 40 |
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