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CA3140AS Datasheet(PDF) 19 Page - Intersil Corporation |
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CA3140AS Datasheet(HTML) 19 Page - Intersil Corporation |
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19 / 19 page ![]() 19 Metallization Mask Layout FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY Typical Performance Curves (Continued) SUPPLY VOLTAGE: VS = ±15V TA = 25 oC FREQUENCY (Hz) 1101 102 103 104 105 100 10 1 1000 102 103 104 105 106 107 FREQUENCY (Hz) 100 80 60 40 20 0 +PSRR -PSRR SUPPLY VOLTAGE: VS = ±15V TA = 25 oC POWER SUPPLY REJECTION RATIO (PSRR) = ∆VIO/∆VS 101 Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90ο with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions. 62-70 (1.575-1.778) 4-10 (0.102-0.254) 60 50 40 30 20 10 0 58-66 (1.473-1.676) 50 40 30 20 10 61 0 60 65 CA3140, CA3140A |
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