AD7933/AD7934

Rev. B | Page 16 of 32

SEQUENCER OPERATION

The configuration of the SEQ0 and SEQ1 bits in the control

register allows use of the sequencer function. Table 11 outlines

the two sequencer modes of operation.

Writing to the Control Register to Program the Sequencer

The AD7933 and AD7934 need 13 full CLKIN periods to

perform a conversion. If the ADC does not receive the full 13

CLKIN periods, the conversion aborts. If a conversion is

aborted after applying 12.5 CLKIN periods to the ADC, ensure

that a rising edge of CONVST or a falling edge of CLKIN is

applied to the part before writing to the control register to

program the sequencer. If these conditions are not met, the

sequencer will not be in the correct state to handle being

reprogrammed for another sequence of conversions and the

performance of the converter is not guaranteed.

Table 10. Analog Input Type Selection

MODE0 = 0, MODE1 = 0

MODE0 = 0, MODE1 = 1

MODE0 = 1, MODE1 = 0

MODE0 = 1, MODE1 = 1

Channel Address

Four Single-Ended

Input Channels

Two Fully Differential

Input Channels

Two Pseudo Differential

Input Channels

Not Used

ADD1

ADD0

0

0

AGND

0

1

AGND

1

0

AGND

1

1

AGND

Table 11. Sequence Selection Modes

SEQ0

SEQ1

Sequence Type

0

0

Select this configuration when the sequence function is not used. The analog input channel selected on each individual

conversion is determined by the contents of ADD1 and ADD0, the channel address bits, in each prior write operation. This

mode of operation reflects the normal operation of a multichannel ADC, without using the sequencer function, where

each write to the AD7933/AD7934 selects the next channel for conversion.

0

1

Not used.

1

0

Not used.

1

1

Use this configuration in conjunction with ADD1 and ADD0, the channel address bits, to program continuous conversions

on a consecutive sequence of channels. The sequence of channels extends from Channel 0 through to a selected final

channel as determined by the channel address bits in the control register. When in differential or pseudo differential mode,