AD7933/AD7934

Rev. B | Page 23 of 32

PARALLEL INTERFACE

The AD7933/AD7934 have a flexible, high speed, parallel

interface. This interface is 10 bits (AD7933) or 12 bits (AD7934)

wide and is capable of operating in either word (W/B tied high)

or byte (W/B tied low) mode. The CONVST signal is used to

initiate conversions and, when operating in autoshutdown or

autostandby mode, it is used to initiate power-up.

A falling edge on the CONVST signal is used to initiate

conversions, and it also puts the ADC track-and-hold into

track. Once the CONVST signal goes low, the BUSY signal goes

high for the duration of the conversion. In between conversions,

conversion is aborted and the track-and-hold goes back into track.

At the end of the conversion, BUSY goes low and can be used to

activate an interrupt service routine. The CS and RD lines are

then activated in parallel to read the 10 bits or 12 bits of

conversion data. When power supplies are first applied to the

device, a rising edge on CONVST is necessary to put the track-

and-hold into track. The acquisition time of 125 ns minimum

must be allowed before CONVST is brought low to initiate a

conversion. The ADC then goes into hold on the falling edge of

after this (see Figure 34). When operating the device in

autoshutdown or autostandby mode, where the ADC powers

down at the end of each conversion, a rising edge on the

CONVST signal is used to power up the device.

12

3

4

5

12

13

14

B

A

DATA

DATA

OLD DATA

DB0 TO DB11

DB0 TO DB11

RD

CS

INTERNAL

TRACK/HOLD

BUSY

CLKIN

CONVST

THREE-STATE

THREE-STATE

WITH CS AND RD TIED LOW

Figure 34. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1)