70353C datasheet(65/76 Pages) MICROCHIP

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DS70353C-page 21-65

Section 21. Enhanced Controller Area Network (ECAN™)

21.11

ECAN INTERRUPTS

The ECAN module generates three different interrupts, each with its own interrupt vector,

interrupt enable control bit, interrupt status flag and interrupt priority control bit. These interrupts

are:

• CiTX – ECAN Transmit Data Request

• CiRX – ECAN Receive Data Ready

• Ci – ECAN Event Interrupt

21.11.1 ECAN Transmit Data Request Interrupt

The transmit data request interrupt represents the transmission of a single word in an ECAN

message through the ECAN Transmit Data register (CiTXD). The user application needs to

assign the ECAN transmit data request interrupt to a DMA channel to automatically transfer

messages from the appropriate device RAM buffers to the ECAN module (CiTXD register).

21.11.2 ECAN Receive Data Ready Interrupt

The receive data request interrupt represents the reception of a single word of an ECAN

message through the ECAN Receive Data register (CiRXD). The user application needs to

assign the ECAN receive data ready interrupt to a DMA channel to automatically transfer

messages from the ECAN module (CiRXD register) to the appropriate device RAM buffers.

21.11.3 ECAN Event Interrupt

The ECAN event interrupt has seven main sources, each of which can be individually enabled.

The Interrupt Flag register (CiINTF) contains the interrupt flags, and the Interrupt Enable register

(CiINTE) contains the enable bits. The Interrupt Flag Code bits (ICODE<6:0>) in the ECAN

Interrupt Code register (CiVEC<6:0>) can be used in combination with a jump table for efficient

handling of interrupts. All interrupts have one source, with the exception of the Error Interrupt.

Any of five error interrupt sources (TX Error Warn, RX Error Warn, TX Error Passive, RX Error

Passive and TX Bus OFF) can set an error interrupt flag. The source of the error interrupt is

determined by reading the CiINTF register.

Figure 21-19 illustrates the ECAN event interrupt generation from various interrupt sources.

Note:

The ICODE<6:0> bits will reflect the highest priority CAN interrupt condition that is

active. For this, the interrupt should be enabled (the IE bit in the CiINTE register

should be set) and the interrupt condition should be active (the IF bit in the CiINTF

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