AP2071 datasheet(7/31 Pages) AKM

7 / 31 page

[AP2071AEN]

MS1607-E-00

- 7 -

2014/03

■ Input Logic Characteristics

(Ta= -30  85C; VIN=2.6  5.5V), SCL, SDA, STROBE, CHARGE, EN, ADDR pins.

Parameter

Symbol

min

typ

max

Unit

High-Level Input Voltage

VIH

1.2

VIN

Low-Level Input Voltage

VIL

0.4

High-Level Output Voltage (SDA pin, Iout= -80A)

VOH

1.4

Low-Level Output Voltage (SDA pin, Iout= 3mA)

VOL

0.4

Input Leakage Current (SCL, SDA, DET pins)

Iin1

-2

A

Pull-down Resistance (STROBE, CHARGE, EN pins)

RIN

200

400

700

kΩ

Control Interface Timing:

SCL Clock Frequency

FSCL

400

kHz

Bus Free Time Between Transmissions

tBUF

1.3

s

Start Condition Hold Time (prior to first clock pulse)

tHD:STA

0.6

s

Clock Low Time

tLOW

1.3

s

Clock High Time

tHIGH

0.6

s

Setup Time for Repeated Start Condition

tSU:STA

0.6

s

SDA Hold Time from SCL Falling (Note 5)

tHD:DAT

s

SDA Setup Time from SCL Rising

tSU:DAT

0.1

s

Rise Time of Both SDA and SCL Lines

0.3

s

Fall Time of Both SDA and SCL Lines

0.3

s

Setup Time for Stop Condition

tSU:STO

0.6

s

Capacitive load on bus

400

Pulse Width of Spike Noise Suppressed by Input Filter

tSP

Power-down & Reset Timing

EN Pulse Width

(Note 6)

tPD

300

Note 5. Data must be held long enough to bridge the 300ns transition time of SCL.

Note 6. The AP2071AEN can be reset by holding the EN pin= “L” upon power-up.

■ Timing Diagram

tHIGH

SCL

SDA

VIH

tLOW

tBUF

tHD:STA

tHD:DAT

tSU:DAT

tSU:STA

Stop

Start

Stop

tSU:STO

VIL

VIH

VIL

tSP

Figure 2. I

2C Bus Mode Timing

tPD

VIL

Figure 3. Enable & Reset Timing

AP2071 Datasheet(PDF) 7 Page - Asahi Kasei Microsystems

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