AN3432

Application constraints

Doc ID 019041 Rev 1

11/24

3

Application constraints

3.1

Constraints linked with the junction box characteristics

●

Solar panel efficiency impact

●

Thermal runaway risk (directly linked with power losses)

●

Compatibility with flash test

●

Thermal test (linked with forward voltage)

●

Thermal cycling test

3.1.1

Power losses

Diode conduction losses

When the diode is conducting in DC mode, its forward voltage causes power losses called

the junction temperature increases. The application note AN604 describes the way to

calculate them:

Equation 10

Considering a solar panel built with 48 cells in series, divided in two sets of 24 cells

protected by one bypass diode each. If one cell of the first set is shadowed while the other

47 cells are fully illuminated, the bypass diode of the shadowed set is conducting, and the

are:

Equation 11

The maximum loss calculations are made with the current through the bypass diode equal

Equation 12

Figure 8 shows the maximum conduction losses for two different types of diodes:

●

STPS20L45 (low forward voltage)

●

STPS2045 (lower leakage current and higher forward voltage than STPS2045)

−

I

I

I

I

)·

T

,

I

(

V

)

T

(

P

j

F

j

cond

=

=

F

F

F

PM

S

)

I

I

)·(

T

,

I

I

(

V

)

T

(

P

s

pm

j

s

pm

F

j

cond

−

−

=

max

)

I

)·(

T

,

I

(

V

)

T

(

P

sc

j

sc

F

j

cond

≤