Layout hints

AN2485

18/29

The third communication line is the PWM_STOP pin (pin #9), which works in conjunction

with the RUN pin (pin #10). The purpose of the PWM_STOP pin is to inhibit the PWM

activity of both the PFC stage and the cascaded DC-DC converter.

The PWM_STOP pin is an open collector, normally open, that goes low if the device is

disabled by a voltage lower than 0.52 V on the RUN pin (#10). It is important to point out that

this function works correctly in systems where the PFC stage is the master and the

cascaded DC-DC converter is the slave or, in other words, where the PFC stage starts first,

powers both controllers and enables/disables the operation of the DC-DC stage. This

function is quite flexible and can be used in different ways. In systems comprising an

auxiliary converter and a main converter (e.g. desktop PC's silver box or Hi-end Flat-TV or

monitor), where the auxiliary converter also powers the controllers of the main converter, the

pin RUN (#10) can be used to start and stop the main converter. In the simplest case, to

enable/disable the PWM controller the PWM_STOP (#9) pin can be connected to either the

output of the error amplifier or, if the chip is provided with it, to its soft-start pin.

The EVAL6563-400W offers the possibility to test the housekeeping functions by connecting

them to the cascaded converter via the series resistors R28, R29, R30. Regarding the

PWM_STOP (#9) pin that is an open collector type, if it needs a pull-up resistor, connect it

close to the cascaded PWM for better noise immunity.

Figure 33.

Interface circuits that let the L6563/A switch on or off a PWM controller

3

Layout hints

The layout of any converter is a very important phase in the design process which may not

always have the necessary attention required by the engineers. Even if it the layout phase

appears time-consuming, a good layout does save time during the functional debugging and

the qualification phases. Additionally, a power supply circuit with a correct layout needs

smaller EMI filters or less filter stages and subsequently provides consistent cost savings.

The L6563 does not need any special attention to the layout, but the general layout rule for

any power converter must be applied carefully. Basic rules using the EVAL6563-400W

schematic as a reference are listed below. They can be used for other PFC circuits having

any power level, working either in FOT or TM control.

1.

Keep power and signal RTN separated. Connect the return pins of components

carrying high current such as C4, C5, sense resistors, C6 and C7 as close as possible.

L6668

PFC_STOP

14

16

Vcc

10 k

Ω

BC557

2.2 k

Ω

L6563

L6563A

Vcc

14

8.2 V

L6563

L6563A

(RUN)

PFC_OK

BC547

L6668

14 PFC_STOP

7

(10)

2.2 k

Ω

8

VREF

100 k

Ω

L6599

PFC_STOP

14

L6563

L6563A

(RUN)

PFC_OK

7

(10)