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AN2487 Datasheet(PDF) 13 Page - STMicroelectronics |
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AN2487 Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 32 page ![]() AN2487 Circuit descriptions 13/32 3.3 Power converter operation The following sections refer to the power converter schematic shown in Figure 6. ST's L6565 (U3) is a transition-mode peak-current controller that drives the FET (Q1) of a flyback converter in response to feedback signals from the converter output and a bootstrap winding. An excellent description of the converter operation is available in the L6565 datasheet, with further detail in ST application note AN1326. Additional design examples are shown in application notes AN1376, AN1439, and AN2252. A design spreadsheet is also available. It is strongly recommended that the designer consult these resources. 3.3.1 Input filtering The power converter has a discontinuous input current. The AC component of this current is supplied locally, by capacitors C3 and C4. C1 and L2 filter the input voltage so that the power source is not polluted. 3.3.2 Startup When the converter initially starts, the L6565 controller (U3) runs from the charge on C7. This charge is quickly depleted, however, and a second power source must start before U3 starves. One of T3's secondaries is used to bootstrap housekeeping power to the L6565. Pin 12 of Transformer T3 feeds R11 and D5 to provide enough current for normal operation. At Q1's first turn-on, current begins to rise linearly (several microseconds) in T3's primary, pins 2 and 3. The current is sensed by the L6565 as the voltage drop across R6, 7, 8, 10, and 19. At the threshold set by the L6565 (more about this in Section 3.3.3: Regulation), the gate drive is removed and the magnetic field generated by T3's primary current is picked up by its secondaries, and fed to the capacitors C7, C11, C12, and C15. The cycle repeats as soon as the field stored in the transformer is depleted, repeating until the capacitors are charged to the desired voltages. 3.3.3 Regulation Eventually (several milliseconds) the load capacitors charge to the desired voltages. The voltage on C11 is monitored by U4, and when U4 conducts sufficiently, it turns on optoisolator ISO1. On the left side of the isolation barrier, ISO1 pulls down on U3's compensation node (pin 2). Peak primary current is controlled directly by the error in output voltage of the 3.3 V output, and inversely by the input voltage. A higher input voltage means that the converter spends less time charging T3's inductance, resulting in a higher power output for the same peak current. This is compensated by U3's internal multiplier, which reduces the peak current setting for higher voltage inputs; so the system gain, current limit and operating point remain roughly constant. Divider R3-R4 sets the voltage input to the L6565's multiplier, which is used to compensate for the faster transformer charge at high voltage. The voltage on pin 2, multiplied by (3 volts less the voltage on VFF), sets the shutoff point for the primary ramp current. |
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