Software

AN4159

14/27

Doc ID 023639 Rev 3

6

Software

6.1

Device register list

6.2

Hints

●

(AVGT,AVGP) = (128,512) (RES=0x7A) is not supported with 25/25 Hz ODR.

–

We recommend to use 0x79 as default value to try in a new system

–

Symptom of wrong configuration can be pressure stuck to 760 mb

●

If the I2C line have glitches and slaves are holding SDA low, a simple I2C error

recovery would be to send 9 stop bits (which will flush the bus), this is usually done by

S/W using the I2C GPIOs resources of the host device. A good practice would be to

check that SDA is high prior to generating a START bit.

Table 3.

Registers address map

Name

Type

Register address

Default

Comment

Hex

Binary

Reserved (do not modify)

00-07 0D - 0E

Reserved

REF_P_XL

R/W

8

1000

0

REF_P_L

R/W

9

1001

0

REF_P_H

R/W

0 A

1010

0

WHO_AM_I

R

0 F

1111

10111011

Dummy register

RES_CONF

R/W

10

10000

11111010

Reserved (do not modify)

11-1F

Reserved

CTRL_REG1

R/W

20

010 0000

0

CTRL_REG2

R/W

21

010 0001

0

CTRL_REG3

R/W

22

010 0010

0

INT_CFG_REG

R/W

23

100011

0

INT_SOURCE_REG

R

24

100100

0

THS_P_LOW_REG

R/W

25

100101

0

THS_P_HIGH_REG

R/W

26

100110

0

STATUS_REG

R

27

010 0111

0

PRESS_POUT_XL_REH

R

28

010 1000

output

PRESS_OUT_L

R

29

010 1001

output

PRESS_OUT_H

R

2A

010 1010

output

TEMP_OUT_L

R

2B

010 1011

output

TEMP_OUT_H

R

2C

010 1100

output

Reserved (do not modify)

2D-2F

Reserved