Functional changes and silicon fixes in STR91xFA

AN2523

12/23

1.

Switch the CPU Master clock source to the OSC by setting bits [1:0] in the

SCU_CLKCNTR register to "10".

2.

Write the new configuration to the SCU_PLLCONF register (write the new P, N and M

values with the PLL_EN enable bit set to "0").

3.

The SCU_PLLCONF register will be updated after the clock has been switched to the

OSC.

4.

If you need the CPU to run at the new PLL clock frequency, write to the

SCU_PLLCONF register again with the new P, N and M values AND the PLL_EN bit set

to "1".

5.

Switch the CPU clock source back to the PLL clock by setting bit[1:0] in the

SCU_CLKCNTR register to "00".

6.

The CPU Master clock will switch automatically from the OSC to the PLL once the

LOCK bit is set. Do not initiate another SCU_PLLCONF register change before the

LOCK bit is set.

6.6

UART

Functional Fix: UART FIFO Overflow Flag

Description: In STR91xF devices, there was a condition in which received data could be

lost due to FIFO overflow, but no indication of the FIFO having overflowed was given. The

condition arose when the FIFO was full, and there was a simultaneous read from the data

register and arrival of new data. In that case the arriving data was not stored, but neither

was an overflow signaled. This has been fixed in STR91xFA.

Impact: Overflow is now properly signaled in all cases where data is lost.

6.7

LVD (Low Voltage Detector)

Functional Fix: LVD and VDD fall time requirement

Description: The STR91xF generates an internal reset signal when the VDD power supply

drops below the LVD (Low Voltage Detect) threshold level. If the rate of fall of VDD voltage is

less than 100 µs as VDD drops from 1.8 V through the 1.4 V threshold, the Low Voltage

Detector logic will not generate the internal reset signal. A workaround solution is to use an

external reset supervisor device to drive the RESET_INn input pin. This problem is fixed in

STR91xFA devices

Impact: If an external reset supervisor device is used as a workaround solution, there is no

need to make any changes and no impact on the STR91xFA.

Functional Fix: LVD logic may hold reset active inappropriately

Description: The LVD logic in STR91xF is able to detect the first occurrence of a VDD or

VDDQ voltage drop that goes below the threshold voltage and it correctly generates an

internal reset signal to the CPU and system. However, for subsequent drops of VDD or

VDDQ voltage below threshold, the LVD logic generates an active internal reset signal, but

the signal remains active (is stuck) even after VDD or VDDQ rises above the threshold

again.

The CPU is hung in a state of reset. A power cycle is needed on VDD to clear the stuck

reset and release the CPU. The problem is fixed in STR91xFA.