AN2523

Functional changes and silicon fixes in STR91xFA

13/23

Impact: The workaround solution for STR91xF is to use an external reset supervisor device.

The STR91xFA will work fine if an external supervisor device is used, it will also work fine if

the device is removed.

6.8

Watchdog

Functional Fix: SCU Control Register control bits will not disable the Watchdog

Description: Watchdog Mode is enabled by setting the WE bit in the WDG_CR register.

Once enabled the Watchdog cannot be disabled by software by clearing the WE bit. In the

System Control Unit, the SCU_PCGR1 and SCU_PRR1 registers also control the clocking

and reset operation of the peripherals, including the Watchdog.

By setting bit 12 of either of the two registers in STR91xF, the Watchdog will lose its clock or

go into reset state and become disabled. This is in contradiction to the Watchdog

specification that once it is enabled, it cannot be disabled by software.

Impact: This problem is fixed on the STR91xFA. There is no need to modify your software

as bit 12 of the two registers become "don't care" bit. Once the Watchdog timer is enabled,

cannot be disabled in the STR91xFA through software control.

If for any reason there is a need to temporarily prevent the watchdog from timing out

(example: EEPROM emulation Flash bank erase), you can change the watchdog

configuration in the STR91xFA to provide a period of time of no watchdog activity. This can

be achieved by switching from the fast 48 MHz PCLK to the slow 32 kHz RTC clock as the

watchdog counter clock source. With the RTC clock, the CPU only needs to update the

watchdog once every ten seconds. Please note once the RTC clock is selected as the

Watchdog counter clock, you cannot switch the clock source to the PCLK as long as the

Watchdog is enabled.

6.9

Motor Control

Functional Fix: PWM Output Polarity

Description: The Motor Control (MC) drives 3-Phase PWM signals and complementary

signals (UH, UL, VH, VL, WH, WL). There are two situations where the MC outputs remain a

constant:

1.

When the Compare register (MC_CMPx) value is greater than the Compare 0 Register

(MC_CMP0), the corresponding PWM output signal is held at '1'.

2.

When the Compare register (MC_CMPx) value is 0, the corresponding PWM output

signal is held at '0'.

The output is a constant at "1" and "0" for the above two configurations when the polarity bits

in the MC_PSR register are set to "0".

The MC outputs (UH and UL, for example) are complementary to each other. But for the

above two configurations in STR91xF the outputs are not complementary and both signals

stay at the same level. This problem is fixed in STR91xFA.

Impact: This problem is fixed in STR91xFA.