AN2523

Enhancements in the STR91xFA devices

19/23

7.3.6

Output values in Emergency Stop and Debug mode

Description: Two control bits, EMS and ESP, are present in the MC_ECR register which,

under particular circumstances, modify the logic values that are output on the six PWM

output pins MC_UH, MC_UL, MC_VH, MC_VL, MC_WH, and MC_WL.

Bit MC_ECR[6] is designated as the Enhanced Motor Stop or EMS control bit. Writing a '1'

to that bit enables an enhanced stop feature that is described below. Bit MC_ECR[1] is the

Enhanced Stop Polarity or ESP bit. The ESP bit selects between normal and inverted output

values under applicable conditions.

The conditions under which these bits affect the PWM output values are complex. However,

they can be summarized as any condition under which normal PWM cycling is halted, or

needs to be halted. The intent is to place all motor drive switches in the OFF state, allowing

the motor to freewheel. The purpose is to protect the motor drive circuits from burnout, not

to apply active braking to stop the motor.

There are three situations in which normal PWM cycling is halted. One is in response to an

active signal on the motor controller's Emergency Stop pin, ESTOP. This signal, mapped

through one of the GPIO interrupt request pins, normally originates with thermal protection

circuitry in the motor drive power electronics. It should not be confused with the signal from

a motor equipment operator's emergency OFF button. The latter calls for active braking of

the motor, which requires continued PWM cycling.

In normal operation, the automatic response to the ESTOP signal is to force the PWM

outputs to zeroes. Zero is assumed to be the value corresponding to the OFF state for the

drive switches. In Enhanced Stop configuration, the value forced to the PWM outputs is

determined by the ESP bit. This allows for the possibility of that a PWM output of '1'

corresponds to the OFF state of a drive switch.

The second situation in which PWM cycling is halted is when software has explicitly stopped

it, by clearing the PWM Counter Enable bit (PCE, bit 5) in register MC_PCR0. In normal

operation, it is essential for the controller software to "safe" the PWM outputs before

disabling the PWM counter. This is done by setting bit 6, the Output Data Selection bit

(ODS) in the Output Peripheral Register MC_OPR. Setting the ODS bit in MC_OPR forces

the six PWM outputs to the XOR of MC_OPR bits [5:0] and MC_PSR bits [5:0]. Failure to set

the ODS bit before disabling the PWM counter could result in burnout of one or more power

switches in the motor drive. As a protection measure, the Enhanced Motor Stop (EMS)

feature has been implemented. If the PWM counter is disabled by software while EMS bit is

enabled, control logic will check the ODS bit. If it is not set, then the PWM outputs are forced

to a safe state in the same manner they would be in response to the ESTOP signal, where

the PWM output values are the XOR of ESP bit and MC_PSR bits[5:0]

The third situation in which PWM cycling is halted is in debug mode, when a hardware break

condition effectively halts the master clock. When EMS bit is set, the Debug Output

Protection bit (DOP) in register MC_ECR enables the PWM outputs to be determined by the

ESP bit.

Impact: Default settings for control registers insure no impact to software developed for

older revisions. Use of the new stop mode features will facilitate software development and

testing for new projects, and result in more robust production code.

7.3.7

Hardware reset of ESC register

In STR91xF devices, after an emergency stop, the firmware writes "4321h" to the MC_ESC

register to restart the PWM and then writes "0000" to clear and re-arm the ESTOP. In