Enhancements in the STR91xFA devices

AN2523

20/23

STR91xFA devices, the clearing of the MC_ESC register is performed by hardware

automatically right after the "4321h" write cycle. This feature is enabled by bit 8 (HRE) in the

new MC_ECR register.

7.4

EMI bus enhancement (BGA 144 package only)

In addition to the LQFP80 and LQFG128 packages available in the STR91xF device family,

STR91xFA devices are offered in a new BGA144 package. Some of the additional I/O pins

available in the BGA package have been used to provide an enhanced External Memory

Interface (EMI). The enhanced interface supports PSRAM type burst mode memories.

7.4.1

Option to configure the new EMI_BCLK signal

Description: A bit was added in the GPIO external memory interface register (SCU_EMI) to

enable/disable the new external EMI_BCLK clock.

Bit 1 was added to the SCU_EMI register, defined as follows:

●

Bit 1 = 0: EMI_BCLK clock out is ENABLED (default)

●

Bit1 = 1: EMI_BCLK clock out is DISABLED

Impact: No impact for STR91xF users.

7.4.2

Option to configure the EMI_WRLn and EMI_WRHn pins

Description: A bit was added in the GPIO external memory interface register (SCU_EMI) to

configure the EMI_WRLn and WMI_WRHn pins.

Bit 2 was added to the SCU_EMI register, defined as follows:

●

Bit 2 = 0: The EMI pins function as EMI_WRLn and EMI_WRHn signals as in STR91xF

devices (default)

●

Bit 2 = 1: The EMI pins function as byte select signals (EMI_LBn and EMI_UBn)

Impact: No impact for STR91xF users.

7.4.3

Interface to PSRAM (burst mode)

Description: The BGA package brings out four new bus signals: EMI_BCLK, EMI_BAA,

EMI_WE and EMI_WAIT. It also provides options to program the EMI_WRLn and

EMI_WRHn signals as EMI_LBn (low byte select) and EMI_UBn (upper byte select). With

the additional bus control signals, the EMI is able to interface directly to a PSRAM.

In PSRAM mode, the EMI bus is configured as a 16-bit, multiplexed bus. The EMI_ALEn

signal is programmed with negative polarity and a 2-clock-wide pulse width to meet the

PSRAM's ADV# (address valid) timing requirement. The EMI address is latched by the

PSRAM at the rising edge of the BCLK while the EMI_ALEn is low. In a read bus cycle, the

EMI bus is tri-stated half a clock after the trailing edge of the EMI_ALE signal. The PSRAM

can then drive the bus when EMI_RDn becomes active.

The EMI bus can access the PSRAM memory array in asynchronous mode or in burst

mode.

However, the EMI bus must be in asynchronous mode when writing to the PSRAM bus

configuration register. The CRE signal, which is required to be high when writing to the