AN2523

Enhancements in the STR91xFA devices

17/23

7.3

Motor control enhancement

Like the ADC controller, the Induction Motor Controller was substantially enhanced for

STR91xFA. Also as with the ADC enhancements, the IMC enhancements were designed for

upward compatibility. There should be no software impact for applications developed for

STR91xF which do not specifically enable the enhancements. The only impacts are for new

applications that choose to make use of the enhancements.

The paragraphs below summarize the new features, and what they enable. The features are

controlled by two new control registers: an Enhance Control Register (MC_ECR) at offset

0x48, and a Lock Register (MC_LOK) at 0x4C.

7.3.1

Double update mode

Description: A Double Update Mode (DUM) is implemented, whereby the three phase

compare registers CMU, CMV, and CMW, along with the PWM clock compare register CM0,

can be updated from their respective preload registers when the PWM counter register hits

its maximum value as well as its minimum value (i.e., zero). The maximum value for the

PWM counter is the value set in the CM0 register. When the PWM counter increments up to

this value, it resets to zero (in classical mode) or reverses direction and begins counting

down to zero (in zero-centered mode).

DUM is only applicable in zero-centered mode, because in classical mode, the maximum

value for the PWM counter register is followed immediately by a clear to zero. The zero

value triggers a normal update cycle, which would make the DUM update on the maximum

counter value redundant.

Impact: When enabled through settings in register MC_ECR, the DUM doubles the

frequency of control value updates to the PWM counter compare registers. This provides a

finer granularity of PWM control. Since the reset values in MC_ECR disable DUM by default,

there is no impact to older software.

7.3.2

Lock bits

Description: A lock register, MC_LOK, has been added to prevent certain control register

bits from being inadvertently modified. A lock bit, once set, prevents its associated control

register bit or bits from being modified. The lock bits are "write once" bits; once a specific

lock bit is set, it cannot be cleared except through a system reset. Its format and a list of

associated control bits are shown below.

LOK0 - Locks PCR0(7,0), DTE and ODTS bits

LOK1 - Locks PCR1(6), EST_EN

LOK2 - Locks PSR(5:0), phase polarity bits PUH, PUL, PVH, PVL, PWH, PWL

LOK3 - Locks OPR(5:0), Output Peripheral Register bits

LOK4 - Locks DTG(5:0), Dead Time Generation Register

Table 5.

Lock register

Name

Address

Offset

15 14 13 12 11 1 0

9

8

7

6

5

lock bits LOKx

MC_LOK

4Ch

Reserved: all bits '0'

4

3

2

1

0