Enhancements in the STR91xFA devices

AN2523

18/23

Impact: Lock bits can be used to simplify software development and add robustness. By

locking critical control register bits, the hardware can be protected from malfunctioning

software. In addition, locks on selected bits enable software to update other bits in the same

control registers without concern for changing the values of the locked bits.

7.3.3

Trigger ADC with PWM

Description: A capability was added to trigger an ADC conversion synchronized with the

PWM counter cycle. Four options are supported:

●

Don't generate an ADC trigger event (default)

●

Generate an ADC trigger when the PWM counter goes to zero ('ZPC')

●

Generate an ADC trigger when the PWM counter reaches its maximum ('CM0')

●

Generate an ADC trigger when the PWM counter goes to zero AND the pulse repetition

down counter is at zero (RDC = 0)

The choice among the above four options is made through the 2-bit ATS field (ADC Trigger

Selection) in the Enhance Control Register MC_ECR.

Impact: The ADC trigger capability enables control of "sensorless" PM or SR motors, in

which rotor position is inferred by tracking the back EMF or the inductance in one or more

stator coils after a drive pulse. It has no impact on software developed for earlier silicon

revisions.

7.3.4

16-bit PWM counter and compare registers

Description: The compare registers CP0, CPU, CPV, and CPW, as well as the PWM

counter itself, have been widened to 16 bits. Bit 5 of the Enhanced Control Register

MC_ECR (the 'EPWM' bit) controls whether or not the additional high order bits are used. In

normal mode, when EPWM = 0 (the default), the additional bits are masked to zero, and

operation of the PWM unit is identical to what it was in STR91xF. When EPWM is set to '1',

the additional high order bits are used. All compares between the PWM counter and the four

compare registers are then full 16-bit compares.

Impact: The wider compare registers enable finer granularity of PWM control, if needed.

They permit a larger step count for one PWM cycle, when the enhanced mode is selected.

For a given PWM cycle frequency, the PCM counter can be clocked at a higher frequency,

by using a smaller value in the PWM clock prescaler register, MC_CPRS. There is no impact

to older software when the default mode (normal) is used.

7.3.5

10-bit dead time counter

Description: The Dead Time Generator register, MC_DTG, has been widened from 6 bits

for the delay count to 10 bits. Whether the old 6-bit width or the new 10-bit width is used is

controlled by bit 4 of MC_ECR, the EDTC bit. When EDTC = 0 (default), the 6-bit width is

used. MC_DTG bits (9:6) are masked to zeros. When EDTC = 1 (enhance mode), all 10

MC_DTG bits are used to count delays.

Impact: Enables larger delay counts to be specified when a faster PWM counter clock is

used. No impact on previously developed software when default mode is used.