Debug management

AN2586

18/28

Doc ID 13675 Rev 7

4.3.2

Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as

dedicated pins immediately usable by the debugger host (note that the trace outputs are not

assigned except if explicitly programmed by the debugger host).

However, the STM32F10xxx MCU implements a register to disable some part or all of the

SWJ-DP port, and so releases the associated pins for general-purpose I/Os usage. This

register is mapped on an APB bridge connected to the Cortex™-M3 system bus. This

register is programmed by the user software program and not by the debugger host.

Table 3 shows the different possibilities to release some pins.

For more details, see the STM32F10xxx (RM0008) and STM32F100xx (RM0041) reference

manuals, available from the STMicroelectronics website www.st.com.

Table 2.

Debug port pin assignment

SWJ-DP pin name

JTAG debug port

SW debug port

Pin

assignment

Type

Description

Type Debug assignment

JTMS/SWDIO

I

JTAG test mode

selection

I/O

Serial wire data

input/output

PA13

JTCK/SWCLK

I

JTAG test clock

I

Serial wire clock

PA14

JTDI

I

JTAG test data input

-

-

PA15

JTDO/TRACESWO

O

JTAG test data output

-

TRACESWO if async trace

is enabled

PB3

JNTRST

I

JTAG test nReset

-

-

PB4

Table 3.

SWJ I/O pin availability

Available Debug ports

SWJ I/O pin assigned

PA13 /

JTMS/

SWDIO

PA14 /

JTCK/

SWCLK

PA15 /

JTDI

PB3 /

JTDO

PB4/

JNTRST

Full SWJ (JTAG-DP + SW-DP) - reset state

X

X

X

X

X

Full SWJ (JTAG-DP + SW-DP) but without

JNTRST

XX

X

X

JTAG-DP disabled and SW-DP enabled

X

X

JTAG-DP disabled and SW-DP disabled

Released