UM0851 datasheet(127/245 Pages) STMICROELECTRONICS

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UM0851

Non-volatile memory device drivers

Doc ID 16604 Rev 2

127/245

#else

err = add_mtd_device( &mtd );

#endif

The hardware control function provides access to the control pins (ALE/CLE) of the NAND

chip. Port address is assigned as per signal type.

static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd,unsigned int ctrl)

{

struct nand_chip *this = mtd->priv;

if (ctrl & NAND_CTRL_CHANGE) {

if (ctrl & NAND_CLE) {

this->IO_ADDR_R = (void __iomem*) SPEAR_START_NAND_FLASH_CMD

this->IO_ADDR_W = (void __iomem*) SPEAR_START_NAND_FLASH_CMD

} else if (ctrl & NAND_ALE) {

this->IO_ADDR_R = (void __iomem *)SPEAR_START_NAND_FLASH_ADDR

this->IO_ADDR_W = (void __iomem *)SPEAR_START_NAND_FLASH_ADDR

} else {

this->IO_ADDR_R = (void __iomem *)SPEAR_START_NAND_FLASH_ADDR

this->IO_ADDR_W = (void __iomem *)SPEAR_START_NAND_FLASH_ADDR

}

if (cmd != NAND_CMD_NONE)

writeb(cmd, this->IO_ADDR_W);

}

How to support a new NAND Flash

In case of a new NAND Flash chip, the following needs to be checked in the device driver:

NAND chip should be listed in drivers/mtd/nand/nand_ids.h.

NAND chip base address should be defined in platform device of arch/arm/mach-

spear600/spear600.c or arch/arm/mach-spear300/spear300.c.

static struct resource nand_resources[] = {

[0] = {

.start = (SPEAR_START_NAND_FLASH_MEM),

.end

= (SPEAR_START_NAND_FLASH_MEM + SPEAR_SIZE_NAND_FLASH_MEM - 1),

.flags = IORESOURCE_MEM,

[1] = {

.start = (SPEAR_START_NAND_FLASH_CMD),

.end

= (SPEAR_START_NAND_FLASH_CMD + SPEAR_SIZE_NAND_FLASH_CMD - 1),

.flags = IORESOURCE_MEM,

[2] = {

.start = (SPEAR_START_NAND_FLASH_ADDR),

.end

= (SPEAR_START_NAND_FLASH_ADDR + SPEAR_SIZE_NAND_FLASH_ADDR - 1),

.flags = IORESOURCE_MEM,

};

NAND chip timings should be correctly programmed in FSMC (done in

spear_nand_fsmc_setup() routine in drivers/mtd/nand/spr_nand_st.c).

/* Fills the structure for Timing and other parameter */

nand_ctrl.wait_on

= FSMC_WAIT_ON;

nand_ctrl.enable_bank = FSMC_BANK_ENABLE;

nand_ctrl.mem_type = FSMC_NAND_MEM;

nand_ctrl.dev_width = FSMC_ACCESS_8;

nand_ctrl.tar = 0x04;

/* Address Latch Low to Read Enable Low */

UM0851 Datasheet(PDF) 127 Page - STMicroelectronics

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