UM0851 datasheet(152/245 Pages) STMICROELECTRONICS

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Accelerator engine device drivers

UM0851

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Doc ID 16604 Rev 2

Accelerator engine device drivers

SPEAr family devices have several embedded engines for processing specific tasks directly

in hardware. These engines accelerate system throughput and off-load the CPU at the

same time.

This section describes the drivers for the following SPEAr accelerator engines:

●

JPEG codec

●

DMA

6.1

JPEG driver

This section describes the JPEG encoder/decoder driver.

6.1.1

Hardware overview

The JPEG codec is connected to the AHB bus. It is able to decode (and encode) image data

contained in memory, from the JPEG (or YUV) format to the YUV (or JPEG) format with or

without header processing.

The codec core implements all the required steps for encoding and decoding image data

according to the JPEG baseline algorithm as specified in ISO/IEC 10918-1. It is specifically

designed to accelerate entropy-coded segment (ECS) encoding and decoding, because this

forms the most computing-intensive part of the baseline JPEG algorithm.

The codec core can enable/disable header processing. If disabled, only the ECS data are

generated / decoded. Support for restart markers is also provided: the codec core

recognizes them in the encoded stream when decoding, and can optionally insert them

when encoding. JPEG encoded data streams decoded by the codec core must be compliant

with the interchange format syntax specified in ISO/IEC 10918-1. JFIF images (the de-facto

standard used to encoded JPEG images) are also supported.

The codec core receives its input data from the FIFO IN buffer. This data can be either:

●

A sequence of minimum coded units (MCU), if the JPGC is used as an encoder from

YUV to JPEG. The MCU is the minimum number of block that can be encoded or

decoded.

●

A stream of entropy coded segments (ECS) if the JPGC is used as a decoder from

JPEG to YUV.

Conversely, output data from the codec core are sent to the FIFO Out buffer as:

●

An ECS stream , whenever the JPGC is working as an encoder

●

An MCU sequence, whenever the JPGC is working as a decoder

The codec controller manages the data flow between the codec core and the FIFO buffers

and between the FIFO buffers and the external RAM. In order to accomplish the latter task,

it uses the DMAC to perform fast data transfers. The overall JPEG codec block diagram is

shown in Figure 40 below.

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