UM0851 datasheet(191/245 Pages) STMICROELECTRONICS

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UM0851

Audio/video drivers

Doc ID 16604 Rev 2

191/245

Audio/video drivers

This section describes all the drivers related to SPEAr audio/video devices.

8.1

LCD controller (CLCD) driver

This section describes the driver for the CLCD controller available in SPEAr600 and

SPEAr300.

8.1.1

Hardware overview

SPEAr300 and SPEAr600 have an ARM PrimeCell Color Liquid Crystal Display Controller

(CLCD) that provides all the necessary control signals to interface directly to a variety of

color and monochrome LCD panels. The CLCD controller fetches the data for display from a

framebuffer memory in RAM and transfers it to the CLCD panel using an internal DMA.

The basic interface of the CLCD controller is shown in Figure 51. The AMBA AHB slave

interface connects the CLCD to the AMBA AHB bus and provides CPU accesses to the

registers. The AMBA AHB master interface transfers display data from a selected slave

(memory) to the PrimeCell CLCD DMA FIFOs.

The output of the panel clock generator block is the panel clock. This is a divided down

version of the CLCD reference clock. A free running reference clock must be provided to

CLCD. Panel Clock Generator can be programmed to match the bit-per-pixel data rate of the

CLCD panel.

The primary function of the timing controller block is to generate the horizontal and vertical

timing panel signals. It also provides panel bias/enable signals. These timings are all

Figure 51.

Block diagram of CLCD controller

AHB slave

interface

AHB master

interface

DMA FIFO and

data formatter

CLCD controller

LCD panel data

CLCD panel

LCD panel control

LCD panel clock

Panel

clock

controller

Timing

controller

Control

and

status

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