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UM0851 Datasheet(PDF) 206 Page - STMicroelectronics |
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UM0851 Datasheet(HTML) 206 Page - STMicroelectronics |
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206 / 245 page ![]() Miscellaneous device drivers UM0851 206/245 Doc ID 16604 Rev 2 9 Miscellaneous device drivers 9.1 General purpose I/O (GPIO) driver This section describes the the GPIO capabilities of the SPEAr embedded MPU family. 9.1.1 Hardware overview A "General Purpose Input/Output" (GPIO) is a flexible software-controlled digital signal. Each GPIO represents a bit connected to a particular pin, or "ball" on Ball Grid Array (BGA) packages. Each input/output can be controlled in two distinct modes: ● Software mode, through an APB interface. ● Hardware mode, through a hardware control interface. The GPIO IP used in the SPEAr family is an ARM PL061 GPIO. SPEAr3xx contains one PL061 instance and SPEAr600 contains four PL061 instances (two local GPIOs in CPU subsystem, one GPIO in the application subsystem and one in the basic subsystem). The main features of the ARM PL061 GPIO are: ● Eight individually programmable input/output pins (default to input at reset) ● Programmable interrupt generation capability on any number of pins (edge and level interrupts). Figure 57. GPIO block diagram The GPIO pin numbers are different in SPEAr3xx and SPEAr600. Refer to Table 53 and Table 54. GPIO pin numbers are different in case of SPEAr3xx and SPEAr600. Input/ output control Mode control multiplexer ID Interrupt control Register block AMBA APB interface Hardware control interface Input/output multiplexer Interrupt detection logic Enable lines Output data Input data |
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