LTC1266CS datasheet(14/20 Pages) LINER

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LTC1266

LTC1266-3.3/LTC1266-5

APPLICATIO S I FOR ATIO

power MOSFET is 15nC. This results in IGATECHG = 6mA

in 200kHz continuous operation for a 2% to 3% typical

mid-current loss with VIN = 5V.

Note that the gate charge loss increases directly with

both input voltage and operating frequency. This is the

principal reason why the highest efficiency circuits

operate at moderate frequencies. Furthermore, it ar-

gues against using larger MOSFETs than necessary to

control I

2R losses, since overkill can cost efficiency as

well as money!

3. I

2R losses are easily predicted from the DC resistances

of the MOSFET, inductor and current shunt. In continu-

ous mode the average output current flows through L

and RSENSE, but is “chopped” between the topside and

bottom-side MOSFETs. If the two MOSFETs have ap-

proximately the same RDS(ON), then the resistance of

one MOSFET can simply be summed with the resis-

tances of L and RSENSE to obtain I2R losses. For

example, if each RDS(ON) = 0.05Ω, RL = 0.05Ω and

RSENSE = 0.02Ω, then the total resistance is 0.12Ω. This

results in losses ranging from 3.5% to 15% as the

output current increases from 1A to 5A. I2R losses

cause the efficiency to roll off at high output currents.

Figure 8 shows how the efficiency losses in a typical

LTC1266 series regulator end up being apportioned. The

gate charge loss is responsible for the majority of the

efficiency lost in the mid-current region. If Burst Mode

operation was not employed at low currents, the gate

charge loss alone would cause efficiency to drop to

discharge COUT until the regulator loop adapts to the

current change and returns VOUT to its steady-state value.

During this recovery time VOUT can be monitored for

overshoot or ringing which would indicate a stability

problem. The Pin 7 external components shown in the

Figure 1 circuit will prove adequate compensation for

most applications.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

% Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc., are the individual losses as a percent-

age of input power. (For high efficiency circuits, only small

errors are incurred by expressing losses as a percentage

of output power).

Although all dissipative elements in the circuit produce

losses, three main sources usually account for most of the

losses in LTC1266 series circuits: 1) LTC1266 DC bias

current, 2) MOSFET gate charge current and 3) I

2R losses.

1. The DC supply current is the current which flows into

VIN (Pin 2). For VIN = 10V the LTC1266 DC supply

current is 170

µA for no load, and increases proportion-

ally with load up to a constant 2.1mA after the LTC1266

series has entered continuous mode. Because the DC

bias current is drawn from VIN, the resulting loss

increases with input voltage. For VIN = 5V the DC bias

losses are generally less than 1% for load currents over

30mA. However, at very low load currents the DC bias

current accounts for nearly all of the loss.

2. MOSFET gate charge current results from switching the

gate capacitance of the power MOSFETs. Each time a

MOSFET gate is switched from low to high to low again,

a packet of charge dQ moves from Power VIN to ground.

The resulting dQ/dt is a current flowing into Power VIN

(Pin 5) which is typically much larger than the DC

supply current. In continuous mode, IGATECHG = f (QN +

QP). The typical gate charge for a 0.05Ω N-channel

Figure 8. Efficiency Loss

IOUT (A)

0.01

LTC1266 • F08

0.03

0.1

0.3

100

GATE CHARGE

LTC1266 IQ

I2R

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