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UPD77112GC Datasheet(PDF) 3 Page - NEC |
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UPD77112GC Datasheet(HTML) 3 Page - NEC |
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3 / 80 page  Serial I/O #1 Peripheral units Data memory unit Operation unit Program control unit Serial I/O #2 Port Host I/O X memory data addressing unit X memory Y memory Interrupt control Loop control stack PC stack PLL MPY 16 × 16 + 40 → 40 ALU (40) R0 - R7 X bus Y bus External memory INT1 - INT4 Note 1 RESET CLKOUT CLKIN WAKEUP Note 1 PLL0 - PLL2 Note 2 Main bus Wait controller IE I/O CPU control Notes 1. The WAKEUP pin is multiplexed with the INT4 pin. With the PD77111 and 77112, the function of the WAKEUP pin can be activated or deactivated by mask option. With the PD77110, this function is always valid. 2. These pins are provided only on the PD77110. The PLL0 and PLL1 pins are multiplexed with the P2 and P3 pins. BSFT Y memory data addressing unit Instruction memory µ µ µ |
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